LTC7803 datasheet(9/34 Pages) AD

9 / 34 page

LTC7802-3.3

Rev. 0

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PIN FUNCTIONS

SENSE1+, SENSE2+ (Pins 1,8): The Positive (+) Input

to the Differential Current Comparators. The ITH pin

voltage and controlled offsets between the SENSE– and

SENSE+ pins in conjunction with RSENSE set the current

trip threshold.

SENSE1–, SENSE2– (Pins 2,7): The Negative (–) Input

to the Differential Current Comparators. The SENSE2–

pin supplies current to its current comparator when it is

greater than INTVCC. When SENSE1– is 3.2V or greater,

it supplies the majority of the sleep mode quiescent cur-

rent instead of VIN, further reducing the input-referred

quiescent current.

FREQ (Pin 3): Frequency Control Pin for the Internal

Oscillator. Connect to ground to set the switching fre-

quency to 350kHz. Connect to INTVCC to set the switching

frequency to 2.25MHz. Frequencies between 100kHz and

3MHz can be programmed using a resistor between the

FREQ pin and ground. Minimize the capacitance on this pin.

MODE (Pin 4): Mode Select Input. This input, which acts

on both channels, determines how the LTC7802-3.3 oper-

ates at light loads. Pulling this pin to ground selects Burst

Mode operation. An internal 100k resistor to ground also

invokes Burst Mode operation when the pin is floating.

Tying this pin to INTVCC forces continuous inductor cur-

rent operation. Tying this pin to INTVCC through a 100k

resistor selects pulse-skipping operation.

RUN1, RUN2 (Pins 5,6): Run Control Inputs for Each

Controller. Forcing either of these pins below 1.1V disables

switching of the corresponding controller. Forcing both of

these pins below 0.7V shuts down the entire LTC7802-

3.3, reducing quiescent current to approximately 1.5µA.

These pins can be tied to VIN for always-on operation. Do

not float the RUN pins.

INTVCC (Pin 17): Output of the Internal 5.1V Low Dropout

Regulator. The driver and control circuits are powered by

this supply. Must be decoupled to ground with a minimum

of 4.7μF ceramic or tantalum capacitor.

EXTVCC (Pin 18): External Power Input to an Internal LDO

Connected to INTVCC. This LDO supplies INTVCC power,

bypassing the internal LDO powered from VIN whenever

EXTVCC is higher than 4.7V. See INTVCC Regulators in the

Applications Information section. Do not exceed 30V on

this pin. Connect this pin to ground if the EXTVCC LDO

is not used.

VIN (Pin 19): Main Bias Input Supply Pin. A bypass capac-

itor should be tied between this pin and GND.

PLLIN/SPREAD (Pin 25): External Synchronization Input

and Spread Spectrum Selection. When an external clock

is applied to this pin, the phase-locked loop will force the

rising TG1 signal to be synchronized with the rising edge

of the external clock. When an external clock is present, the

regulators operate in pulse-skipping mode if it is selected

by the MODE pin, or in forced continuous mode otherwise.

When not synchronizing to an external clock, tie this input

to INTVCC to enable spread spectrum dithering of the oscil-

lator or to ground to disable spread spectrum.

BG1, BG2 (Pins 20,16): High Current Gate Drives for

Bottom (Synchronous) N-Channel MOSFETs. Voltage

swing at these pins is from ground to INTVCC.

BOOST1, BOOST2 (Pins 21,15): Bootstrapped Supplies to

the Top Side Floating Drivers. Connect capacitors between

the corresponding BOOST and SW pins for each channel.

Also connect Schottky diodes between the BOOST1 and

INTVCC pins and the BOOST2 and INTVCC pins. Voltage

swing at the BOOST pins is from INTVCC to (VIN + INTVCC).

SW1, SW2 (Pins 22,14): Switch Node Connections to

Inductors.

TG1, TG2 (Pins 23,13): High Current Gate Drives for Top

N Channel MOSFETs. These are the outputs of floating

drivers with a voltage swing of INTVCC superimposed on

the switch node voltage SW.

PGOOD1, PGOOD2 (Pins 24,12): Open-Drain Power

Good Outputs. The VOUT1, VFB2 pins are monitored to

ensure that VOUT1,2 are in regulation. When VOUT is not

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