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HCMS-2913 Datasheet(PDF) 9 Page - Broadcom Corporation.

Part # HCMS-2913
Description  High Performance CMOS 5횞7 Alphanumeric Displays
PDF  17 Pages
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Manufacturer  BOARDCOM [Broadcom Corporation.]
Direct Link  http://www.broadcom.com
Logo BOARDCOM - Broadcom Corporation.

HCMS-2913 Datasheet(HTML) 9 Page - Broadcom Corporation.

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9
HCMS-29xx Write Cycle Diagram
Control Word 0
Loading the Control Register with D7 = Logic low se-
lects Control Word 0 (see Table 2). Bits D0-D3 adjust the
display brightness by pulse width modulating the LED
on-time, while Bits D4-D5 adjust the display brightness
by changing the peak pixel current. Bit D6 selects normal
operation or sleep mode.
Sleep mode (Control Word 0, bit D6 = Low) turns off the
Internal Display Oscillator and the LED pixel drivers. This
mode is used when the IC needs to be powered up, but
does not need to be active. Current draw in sleep mode
is nearly zero. Data in the Dot Register and Control Words
are retained during sleep mode.
Control Register
The Control Register allows software modification of the
IC’s operation and consists of two independent 7-bit
control words. Bit D7 in the shift register selects one of
the two 7-bit control words. Control Word 0 performs
pulse width modulation brightness control, peak pixel
current brightness control, and sleep mode. Control
Word 1 sets serial/simultaneous data out mode, and
external oscillator prescaler. Each function is indepen-
dent of the others.
Control Register Data Loading
Data is loaded into the Control Register, MSB first, ac-
cording to the procedure shown in Table 1 and the
Write Cycle Timing Diagram. First, RS is brought to logic
high and then CE is brought to logic low. Next, each
successive rising CLK edge will shift in the data on the
DIN pin. Finally, when 8 bits have been loaded, the CE
line is brought to logic high. When CLK goes to logic
low, new data is copied into the selected control word.
Loading data into the Control Register takes place while
the previous control word configures the display.
NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
TRSS
RSH
T
TCLKCE
CES
T
CLKH
T
CLKL
T
CEH
T
DS
T
DH
T
CEDO
T
DOUT
T
DOUTP
T
PREVIOUS DATA
NEW DATA
NEW DATA LATCHED HERE[1]
CE
RS
CLK
DIN
LED OUTPUTS,
CONTROL
REGISTERS
(SIMULTANEOUS)
OUT
D
D
(SERIAL)
OUT
2
1
3
4
11
12
6
7
8
10
9
5



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