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ICS952301

Advance Information

0673—07/09/02

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS952301. It is used to turn off the PCICLK clocks for low power operation.

PCI_STOP# is synchronized by the ICS952301 internally. The minimum that the PCICLK clocks are enabled

(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a

full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one

PCICLK clock.

CPU_STOP# Timing Diagram

CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.

CPU_STOP# is synchronized by the ICS952301.The minimum that the CPUCLK is enabled (CPU_STOP# high pulse)

is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be

stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency

is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may

exist. This signal is synchronized to the CPUCLKs inside the ICS9248-192.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952301 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the ICS952301.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

PCICLK

CPUCLK

PCI_STOP# (High)

CPU_STOP#

PD# (High)

INTERNAL

CPUCLK