CY28342ZCT datasheet(13/22 Pages) CYPRESS

13 / 22 page

CY28342

Document #: 38-07349 Rev. *A

Page 13 of 22

CPU_STP# Clarification

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting of the CPU output clocks

while the rest of the clock generator continues to function.

CPU_STP# Assertion

When CPU_STP# pin is asserted, all CPU outputs that are set

with the SMBus configuration to be stoppable via assertion of

CPU_STP# will be stopped after being sampled by two falling

CPU clock edges. The final state of the stopped CPU signals

is CPU = HIGH and CPU0# = LOW. There is no change to the

output drive current values during the stopped state. The CPU

is driven HIGH with a current value equal to (Mult0

“select”) × (Iref), and the CPU# signal will not be driven. Due

to external pull-down circuitry, CPU# will be LOW during this

stopped state.

CPU_STP# Deassertion

The deassertion of the CPU_STP# signal will cause all CPU

outputs that were stopped to resume normal operation in a

synchronous manner. Synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock

resumes. The maximum latency from the deassertion to active

outputs is no more than two CPU clock cycles.

CPU_STP#

CPUT

CPUC

Figure 1. Assertion CPU_STP# Waveform

CPU_STP#

CPUT

CPUC

CPUT

CPUC

Figure 2. Deassertion CPU_STP# Waveform

CY28342ZCT Datasheet(PDF) 13 Page - Cypress Semiconductor