LM27262 datasheet(18/22 Pages) NSC

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Component Selection (Continued)

MAX = 1.526V

There will also be an initial step equal to

∆I

OUT x ESR, which

in our example will be approximately 41mV. The two effects

are not entirely additive since the voltage across the ESR is

decreasing as the capacitor gets charged. Therefore, the

actual peak voltage will be somewhat less than the 1.567V

that simple addition would predict. In general, it’s a good

idea to provide pads for a couple of extra capacitors on the

layout in case a little extra decoupling proves necessary.

The output ripple currents of multiphase regulators tend to

cancel to some degree. This greatly reduces the demand on

the output capacitors. Figure 6 allows a simple estimate to

be made of the total output ripple current based on the

number of phases and the nominal duty cycle. Simply pick

the worst case (highest ripple) operating point off the curve

and multiply by the single channel pk-pk ripple current. The

expected pk-pk output ripple voltage will be approximately:

Vrip = Irip x ESR

This simplified equation ignores the reactive term of the

capacitor’s impedance. With any kind of electrolytic capaci-

tor it’s generally safe to ignore the capacitive reactance term

since it will prove to be negligible compared to the ESR.

CALCULATING THE INDUCTOR RIPPLE CURRENT

The LM27262 operates at a switching frequency of 300kHz

per phase. The high side switch on time is therefore the

period, 3.33µs, multiplied the duty factor, V

OUT/VIN. During

this time the inductor is connected between the input and the

output, so inductor current ramps positive during this time.

The peak-peak ripple current

∆I is approximately equal to:

∆I = 3.3µs x (V

OUT -VOUT

2 /V

IN)/L

Continuing our example and assuming a maximum input of

12V:

∆I = 3.3µs x (1.5V - 1.5V2 / 12V) / 0.50µH

∆I = 8.66A

IN = 1.5A

With a maximum phase current of 17.5A this is a bit higher

than desired so a little larger inductor value may be in order.

Assuming a 35% ripple current and 17.5A/phase:

L = 3.3µs x (1.5V - 1.5V

2 / 12V) / 6.125

L = 0.71µH

If the larger value of inductor is used, it may be necessary to

go back and recalculate some of the early assumptions.

The peak current seen by the inductors will be the maximum

DC current plus one half of the ripple current. The maximum

DC current should be assumed to be approximately 10% to

15% greater than the maximum anticipated load current to

allow for short circuit current. The inductors must not hard

saturate in a fault. Again from our example, 110% of 17.5A

plus one half of the 6.125A peak-peak ripple current yields a

peak inductor current of 22.3A. There will usually be two

current ratings associated with an inductor. One is the aver-

age current rating and the second is the saturation current.

Only the saturation current need be considered for short

circuit limiting. The sustained DC current is the 110% of

17.5A or roughly 19A in this example. If over current latch off

is employed, only the 17.5A steady state current need be

considered since the inductor’s steady state current rating is

basically a thermal limitation.

MOSFET SELECTION

The choice of power FETs is driven primarily by efficiency or

thermal considerations. There are two main loss compo-

nents to consider, conduction losses and switching losses.

The switching losses are primarily due to parasitics in the

FETs and are very hard to estimate with any degree of

accuracy. The conduction losses are much easier to charac-

terize. The switching losses in the low-side FET are very low

since it’s essentially a zero-voltage switched device. How-

ever, the high-side device’s switching losses are usually

larger than its conduction losses. The primary contributor to

high-side FET switching losses is related to the reverse

recovery characteristics of the low-side FET’s body diode.

During the small dead band where both FETs are off every

cycle, the low-side FET’s body diode will carry the inductor

current. The problem is that the body diode exhibits a sig-

nificant reverse recovery time, trr. During this time, the FET

looks like a short circuit. When the high-side FET is subse-

quently turned on, there is a shoot through path from the

input supply to ground. A larger high-side FET will tend to

exhibit a larger shoot through current. Therefore, it is unde-

sirable to oversize the high-side device. Since the low-side

device looks like a short, the entire supply voltage is im-

pressed across the high–side device, along with a simulta-

neous high current. The result is very high momentary power

dissipation. The total power lost is a direct function of the

switching frequency.

As a starting point, assume that about 1⁄2 of the switcher’s

total losses will take place in the MOSFETs. If from our prior

example, we assume a desired 90% efficiency at full load,

the FET losses are therefore 5% of the full output power or

5.25W. Since we have four phases, that works out to 1.31W/

phase. This is divided between the upper and lower FETs.

Since the step down ratio is large, the low side FETs will be

on for most of the period. The low-side FET conduction loss

is I

2 x Rds(on) * (1-DF), where DF is the duty factor, V

OUT/

IN. The worst-case dissipation occurs at high input line

voltage. We’ve assumed 12V for our example. Allowing 50%

of the total FET loss to the low-side switch gives us a

dissipation of 0.66W x Rds(on) . This will usually result in a

conservative design. Solving for Rds(on) :

Rds(on) = P

dis/(I

2 x (1- V

OUT/VIN)) Rds(on) = 0.65W/(17 x

2x (1-1.5V/12V))

Rds(on) = 2.4m

Ω

A pair of Si7356 MOSFETs in parallel is very close to this.

These are trench devices with excellent thermal character-

istics as well.

The high-side FET on-resistance is calculated similarly, but

allow one half of the dissipation to switching losses. There-

fore the allowable conduction loss is approximately 0.325W.

Rds(on) = Pdis/(I2 x (V

OUT/VIN))

Rds(on) = 0.325W/(17x 5A

2 x 1.5/12V))

Rds(on) = 8.5m

Ω

A pair of Si7392 FETs will meet this requirement.

GATE DRIVE RTEQUIREMENTS

Energy for the high side gate drives is stored in the boost

capacitors, which in turn are powered by the 5V supply. The

charge stored in each boost capacitor should be between 10

times and 20 times the Qg specified for the high-side FETs.

For the example given, the specified maximum Qg is 15nC.

There will be two of these devices in parallel so the com-

bined gate charge is 30nC. Therefore, the charge stored on

the boost capacitor should be a minimum of 300nC.

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