OPA210 datasheet(23/42 Pages) TI

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9 Power Supply Recommendations

The OPAx210 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –

40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature

are presented in Section 6.7.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including

the following guidelines:

• Noise from the amplifier can propagate into other analog circuits through the power pins of the amplifiers.

Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close

to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply

applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than running

in parallel with the noisy trace.

• Place the external components as close to the device as possible.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• For best performance, clean the PCB following board assembly.

• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, bake the PCB to remove moisture introduced into

the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30

minutes is sufficient for most circumstances.

10.2 Layout Example

OUT A

±IN A

+IN A

V±

OUT B

V+

+IN B

VS+

VS±

GND

Ground (GND) plane on another layer

VOUT A

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Place components

close to device and to

each other to reduce

parasitic errors

Use low-ESR,

ceramic bypass

capacitor

GND

Use a low-ESR,

ceramic bypass capacitor

±IN B

Figure 10-1. OPA2210 Layout Example

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OPA210, OPA2210

SBOS924G – SEPTEMBER 2018 – REVISED APRIL 2021

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