LTC4367 datasheet(19/24 Pages) AD

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LTC4381

Rev. 0

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APPLICATIONS INFORMATION

Figure 7. Surge Stopper with Output Clamped Below 60V with 100V/1A/400ms Overvoltage Protection

Design Example 2

A second design example has the following specifications:

VIN = 24VDC with a transient of 100V peak and a dura-

tion of 400ms like a load dump waveform, VOUT ≤ 60V,

load of 1A.

There are a few methods to clamp VOUT to less than 60V,

we can use the LTC4381-2 by connecting SEL pin to IN to

clamp VOUT to 47V. Or we can use a LTC4381-4 and clamp

VCC to <50V. A third method is to regulate VOUT directly

using a 56V Zener and NPN as shown in Figure 7. This

method gives a slightly tighter VOUT clamp at an expense

of more external components.

Since IN can goes as high as 100V, a clamp at VCC pin is

needed to limit it to <80V. Use Zener CMZ5945B as D1

which limits VCC to <68V.

The maximum current through R1 into D1 during tran-

sients is then calculated by Equation 28.

ID1 =

100V – 68V

100k

= 0.32mA

(28)

Power dissipated in D1 is 22mW.

RSNS

40m

332k

100k

RDRN

100k

CTMR

4.7µF

COUT

22µF

68V

CMZ5945B

DRN

VCC

SEL

GND

4381 F07

TMR

SRC

SNS

OUT

LTC4381-4

GATE

GFET

VIN

100VPK

100

47nF

VOUT

CLAMPED

AT 56.7V/1A

FLT

MMBT5551-7-F

56V

CMZ5943B

10k

RDRN is chosen to produce a current into the DRN pin of

less than 1mA, during the maximum overvoltage transient

event (Equation 29).

RDRN =

100V – 24V

1mA

= 76kΩ

(29)

100kΩ is chosen to give enough margin.

The MOSFET stress can be calculated using the prototyp-

ical transient waveform shown in Figure 3 using tr = 5ms,

VPK = 100V and τ = 200ms (Equation 30).

= VREG – VIN = 56.7V − 24V = 32.7V

= VPK – VIN = 100V − 24V = 76V

P t

= ILOAD

− a)3

τ 2a2In

+ 3a2 + b2 − 4ab

⎛

⎝⎜

⎞

⎠⎟

⎡

⎣

⎢

⎤

⎦

⎥

1/2

P t = 9.3W s

(30)

This is within the LTC4381 SOA limit of 10W√s.

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