Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Data MSByte

(2)

1

Start By

Controller

ACK By

Target

ACK By

Controller

From

Target

1

9

1

9

SDA

SCL

0

0

A3

D15 D14 D13

D12

D11 D10

D9

D8

A2

A1

A0

Frame 3 Data LSByte

(2)

Stop

No ACK By

(3)

Controller

From

Target

1

9

D7

D6

D5

D4

D3

D2

D1

D0

A.

The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 7-1.

B.

Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 7-4.

C.

ACK by the controller can also be sent.

D.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-3. Timing Diagram for Read Word Format

Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Register Pointer Byte

1

Start By

Controller

ACK By

Target

ACK By

Target

1

9

1

9

SDA

SCL

0

0

A3

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

Stop

A.

The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 7-1.

Figure 7-4. Typical Register Pointer Set

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The controller

generates a start condition followed by a valid serial byte containing high-speed (HS) controller code 00001XXX.

This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The

device does not acknowledge the HS controller code, but does recognize it and switches its internal filters to

support 2.94-MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as

the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions

to maintain the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the

device to support the F/S mode.

7.5.4 General Call Reset

A general call reset to multiple devices is implemented by addressing the general call address 0000 000, with

the last R/W bit set to 0. This is then followed by the following data byte 0000 0110 (06h).

On receiving this 2-byte sequence, all devices designed to respond to the general call address will reset. All

INA236 devices on the bus will do a soft reset operation and return to the default power-up conditions

7.5.5 General Call Start Byte

A general call ADC conversion start command to multiple INA236 devices is implemented by addressing the

general call address 0000 000, with the last R/W bit set to 1. No other data bytes are required. Be aware that

other devices in the bus that use general call start commands on the bus will also trigger a start of conversion.

7.5.6 SMBus Alert Response

The INA236 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides

a quick fault identification for simple targets. When an Alert occurs, the controller can broadcast the Alert

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INA236

SBOSA81 – MAY 2021

Copyright © 2021 Texas Instruments Incorporated

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