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Table 7-10. Mask/Enable Register Field Descriptions

Bit

Field

Type

Reset

Description

SOL (Shunt Over-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the shunt voltage

conversion result exceeds the value programmed in the LIMIT register

This bit will clear in transparent mode as long as the limit is not exceeded.

In Latched mode the ALERT pin clears by reading this register. External ALERT

can also be cleared by SMB Alert Response to this register.

SUL (Shunt Under-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the shunt voltage

conversion result is below the value programmed in the LIMIT register.

Cannot be set if Shunt overlimit is set.

This bit will clear in transparent mode as long as the limit is not exceeded.

In Latched mode clears by reading this register. External ALERT is cleared by

SMB Alert Response.

BOL (Bus Over-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the bus voltage

conversion result exceeds the value programmed in the LIMIT register

Cannot be set if Shunt overlimit or Shunt underlimit is set.

This bit will clear in transparent mode as long as the limit is not exceeded.

In Latched mode clears by reading this register. External ALERT is cleared by

SMB Alert Response.

BUL (Bus Under-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the bus voltage

conversion result is below the value programmed in the LIMIT register

Cannot be set if Shunt over limit, Shunt under limit or Bus over limit is set.

This bit will clear in transparent mode as long as the limit is not exceeded.

In Latched mode clears by reading this register. External ALERT is cleared by

SMB Alert Response.

POL (Power Over-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the power result

exceeds the value programmed in the LIMIT register

Cannot be set if Shunt over limit, Shunt under limit, Bus over limit or Bus under

limit is set.

This bit will clear in transparent mode as long as the limit is not exceeded.

In Latched mode clears by reading this register. External ALERT is cleared by

SMB Alert Response.

CNVR (Conversion

Ready)

R/W

Setting this bit high configures the ALERT pin to be asserted when the

Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready

for the next conversion.

0b = Disable conversion ready flag on ALERT pin

1b = Enables conversion ready flag on ALERT pin

9-6

Reserved

0000b

MemError

CRC or ECC error

AFF (Alert Function

Flag)

Alert Function Flag -While only one Alert Function can be monitored at the

ALERT pin at a time, the Conversion Ready can also be enabled to assert the

ALERT pin. Reading the Alert Function Flag following an alert allows the user to

determine if the Alert Function was the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit

clears only when the Mask/Enable Register is read. When the Alert Latch Enable

bit is set to Transparent mode, the Alert Function Flag bit is cleared following the

next conversion that does not result in an Alert condition.

CVRF (Conversion

Ready Flag)

Clears by starting a new single shot conversion, by reading this register or by

SMB alert response.

OVF (Math Over-flow)

This bit is set to '1' if an arithmetic operation resulted in an overflow error. It

indicates that current and power data may be invalid.

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INA236

SBOSA81 – MAY 2021

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