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INA236 Datasheet(PDF) 18 Page - Texas Instruments |
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INA236 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 32 page ![]() Table 7-10. Mask/Enable Register Field Descriptions (continued) Bit Field Type Reset Description 1 APOL (Alert Polarity) R/W 0b Alert Polarity bit sets the Alert pin polarity. 0b = Normal (Active-low open drain) 1b= Inverted (active-high ) 0 LEN (Alert Latch Enable) R/W 0b When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit resets to the idle states when the fault condition has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remains active following a fault until this register flag has been read. This bit must be set to use the I2C Alert Response function. 0b = Transparent 1b = Latched Alert pin 7.6.1.8 Alert Limit Register (Address = 7h) [reset = 0000h] The alert limit register is shown in Table 7-11. Return to the Summary Table. Table 7-11. Alert Limit Register Field Descriptions Bit Field Type Reset Description 15-0 LIMIT R/W 0000h 2’s complement value for the Shunt Over Voltage limit. The units are the same as the MSB’s of the targeted register 7.6.1.9 Manufacturer ID Register (Address = 3Eh) [reset = 5449h] The manufacturer ID register is shown in Table 7-12. Return to the Summary Table. Table 7-12. MANUFACTURE_ID Register Field Descriptions Bit Field Type Reset Description 15-0 MANUFACTURE_ID R 5449h Reads back TI in ASCII 7.6.1.10 Device ID Register (Address = 3Fh) [reset = A080h] The Device ID register is shown in Table 7-13. Return to the Summary Table. Table 7-13. DEVICE_ID Register Field Descriptions Bit Field Type Reset Description 15-3 DIEID R A080h Stores the device identification bits 3-0 Reserved R 0h Always read 0 INA236 SBOSA81 – MAY 2021 www.ti.com 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA236 |
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