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WM8774IFT Datasheet(PDF) 10 Page - Wolfson Microelectronics plc |
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WM8774IFT Datasheet(HTML) 10 Page - Wolfson Microelectronics plc |
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10 / 42 page ![]() WM8774 Product Preview PP Rev 1.0 June 2002 10 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK DOUT ADCLRC DIN DACLRC WM8774 CODEC DVD Controller Figure 4 Audio Interface – Slave Mode BCLK DACLRC/ ADCLRC t BCH t BCL t BCY DIN DOUT t LRSU t DS t LRH t DH t DD Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns DACLRC/ADCLRC set-up time to BCLK rising edge tLRSU 10 ns DACLRC/ADCLRC hold time from BCLK rising edge tLRH 10 ns DIN set-up time to BCLK rising edge tDS 10 ns DIN hold time from BCLK rising edge tDH 10 ns DOUT propagation delay from BCLK falling edge tDD 0 10 ns Table 3 Digital Audio Data Timing – Slave Mode Note: 1. ADCLRC and DACLRC should be synchronous with MCLK, although the WM8774 interface is tolerant of phase variations or jitter on these signals. |
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