WM2130

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.2 April 2001

12

AVDD/2

AIN

REFSENSE

+FS

-FS

REFTS

REFBS

VM

VM

DC SOURCE =VM

REFTF

REFBF

0.1µF

0.1µF

0.1µF

10µF

+

-

MODE

Figure 11 Centre Span Mode, 2V Reference Span

TOP/BOTTOM MODE (MODE = AVDD)

Top/Bottom mode is enabled by connecting the MODE pin to AVDD. In this mode, the ADC

Reference voltages REFTF and REFBF are generated by the internal reference buffer from the

externally supplied voltages REFTS and REFBS. Only single-ended input is possible in

TOP/BOTTOM Mode.

REFTS

REFBS

AIN

REFTF =

AVDD + (REFTS - REFBS)

ADC

CORE

INTERNAL

REFERENCE

BUFFER

REFBF =

AVDD - (REFTS - REFBS)

SAMPLE

AND

HOLD

-1/2

+1

-1/2

Figure 12 ADC Reference Generation in Top/Bottom Mode

The voltage difference between REFTS and REFBS should equal the peak-to-peak input signal

amplitude. A smaller voltage difference would give rise to out-of-range conditions, whereas a larger

one would not fully utilise the ADC resolution. The average of REFTS and REFBS must be the AIN

Typically, REFSENSE is tied to AVDD to disable the on-chip reference generator, but the user can

also choose to use its output to drive either REFTS or REFBS.

AVDD

AIN

REFSENSE

REFTF

REFBF

+FS

-FS

REFTS

REFBS

MODE

DC SOURCE =

VM + [(FS+) - (FS-)]* GAIN/2

DC SOURCE =

VM - [(FS+) - (FS-)]* GAIN/2

0.1µF

10µF

0.1µF

0.1µF

Figure 13 Top/Bottom Mode (Reference Generator Disabled)