Production Data

WM2130

WOLFSON MICROELECTRONICS LTD

PD Rev 1.2 April 2001

19

DIGITAL OUTPUT LOADING AND CIRCUIT BOARD LAYOUT

The WM2130 outputs are capable of driving rail-to-rail with up to 20pF of load per pin at 30MHz clock

and 3V digital supply. Minimising the load on the outputs will improve WM2130 signal-to-noise

performance by reducing the switching noise coupling from the WM2130 output buffers to the internal

analogue circuits. The output load capacitance can be minimised by buffering the WM2130 digital

outputs with a low input capacitance buffer placed as close to the output pins as physically possible,

and by using the shortest possible tracks between the WM2130 and this buffer.

Noise levels at the output buffers, which may affect the analogue circuits within WM2130, increase

with the digital supply voltage. Where possible, consider using the lowest DVDD that the application

can tolerate.

Use good layout practices when designing the application PCB to ensure that any off-chip return

currents from the WM2130 digital outputs (and any other digital circuits on the PCB) do not return via

the supplies to any sensitive analogue circuits. The WM2130 should be soldered directly to the PCB

for best performance. Socketing the device will degrade performance by adding parasitic socket

inductance and capacitance to all pins.

USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2130

•

Choose differential input mode for best distortion performance.

•

Choose a 2V ADC input span for best noise performance.

•

Choose a 1V ADC input span for best distortion performance.

•

Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled

power supply and short PCB traces.