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PRINCIPLES OF OPERATION

ANALOG INPUT

AIN−

0

4095

2V

MODE 2, CON[1:0] = 10

AIN−

0

4095

1V

MODE 1, CON[1:0] = 01

AIN+

AIN+

THS1215

SLAS292A – MARCH 2001 – REVISED MARCH 2004

The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC CORE, where

reference generation. The ADC reference voltages come from either the internal reference buffer or completely

generation.

CON0 and CON1 as described below, select the input configuration mode or place the device in power-down

state. The ADC core drives out through output buffers to the data pins D0 to D11. The output buffers can be

disabled by the OE pin.

A single, sample-rate clock (15 MHz maximum) is required at pin CLK. The analog input signal is sampled on the

rising edge of CLK, and corresponding data is output after the fifth following rising edge.

The THS1215 can operate in differential Mode 1 or differential Mode 2, controlled by the configuration pins

CON0 and CON1 as shown in Table 1. Mode 0 places the THS1215 in power-down or standby state for reduced

power consumption.

Table 1. Input Modes of Operation

MODE

CON1

CON0

MODE OF OPERATION

0

0

0

Device powered down

1

0

1

Differential mode

× 1

2

1

0

Differential mode

× 0.5

3

1

1

Not used

Modes 1 and 2 are shown in Figure 14.

Figure 14. Input Mode Configurations

The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of the

sample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. The

Table 2. Input Mode Switching

(AIN+) – (AIN-)

(AIN+) – (AIN-)

MODE

CON1

CON0

S/H GAIN

MIN

MAX

1

0

1

–1 V

1 V

×1

2

1

0

-2 V

2 V

×0.5

11