THS1215CPWR datasheet(12/22 Pages) TI

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SIGNAL PROCESSING CHAIN (Sample and Hold, ADC)

SAMPLE

AND

HOLD

AIN−

AIN+

−1

VP+

VP−

REFT

REFB

ADC

CORE

Sample and Hold

Analog-to-Digital Converter

Analog input

THS1215

SLAS292A – MARCH 2001 – REVISED MARCH 2004

Table 2 assumes that the delta in ADC reference voltages VREFT and VREFB is set to 1 V, i.e., VREFT – VREFB = 1

V. Note that VREFB and VREFT can be set externally, which will scale the numbers given in this table.

The user-chosen operating configuration and reference voltages determine what input signal voltage range the

THS1215 can handle.

The following sections explain both the internal signal flow of the device and how the input signal span is related

to the ADC reference voltages, as well as the ways in which the ADC reference voltages can be buffered

internally or externally applied.

Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.

Figure 15. Analog Input Signal Flow

The differential sample and hold processes AIN with respect to the voltages applied to the REFT and REFB pins,

to give a differential output (VP+) – (VP–) = VP given by:

•

VP = (AIN+) – ( AIN–)

No matter what operating configuration is chosen, VP is digitized against ADC reference voltages VREFT and

VREFB. The VREFT and VREFB voltages set the analog input span limits FS+ and FS–, respectively. Any voltages at

AIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high when

the conversion result is output.

A first-order approximation for the equivalent analog input circuit of the THS1215 is shown in Figure 16. The

equivalent input capacitance CI is 5 pF typical. The input must charge/discharge this capacitance within the

sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides

the charging current through the switch resistance RSW (200 Ω) of S1 and quickly settles. In this case the input

impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold

capacitor requires no input current and the equivalent input impedance is high.

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