DK2000 High-Performance Demo Kit Motherboard

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The Slot LED registers control the LEDs on the daughter cards as follows:

00

LED is OFF

01

LED is ON and is RED

10

LED is ON and is GREEN

11

LED is OFF

The FPGA register holds the address of the FPGA on the board. This is reserved for future use. The FPGA is

unpopulated on most boards.

CS11. Chip select 11 is used by the EPLD. The current EPLD implementation has the registers defined in Table 7.

Table 7. Chip Select 11 Mapping

ADDRESS OFFSET

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

0x00

EPLD Version Number

0x01

UPDATE

TAG_CLR

FLUSH

MISS_INH

Unused

UPDATE: Reset to 0. When 0, inhibits updating of the L2 cache.

TAG_CLR: Reset to 0. When 0, clears the L2 cache Tag.

FLUSH:

Reset to 0. When 0, flushes the L2 cache.

MISS_INH: Reset to 0. When 0, forces all L2 cache accesses to miss.

MPC8260 I/O Pin Mapping

The MPC8260 has 120 I/O pins that can be configured for special-purpose or general-purpose I/O. The DK2000

development platform takes advantage of as much of the I/O capability as possible. Table 8 shows how the I/O

pins are connected on the DK2000 board. Table 9 and Table 10 add details on some of the special-purpose pin

assignments.