PCIMX6D4AVT12AD datasheet(5/170 Pages) NXP

5 / 170 page

Introduction

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018

NXP Semiconductors

Figure 1. Part Number Nomenclature—i.MX 6Quad and i.MX 6Dual

1.2

Features

The i.MX 6Dual/6Quad processors are based on Arm Cortex-A9 MPCore platform, which has the

following features:

•

Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone®)

•

The core configuration is symmetric, where each core includes:

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The Arm Cortex-A9 MPCore complex includes:

•

General Interrupt Controller (GIC) with 128 interrupt support

•

Global Timer

•

Snoop Control Unit (SCU)

•

1 MB unified I/D L2 cache, shared by two/four cores

•

Two Master AXI (64-bit) bus interfaces output of L2 cache

Part differentiator

Industrial with VPU, GPU, no MLB

Automotive with VPU, GPU

Consumer with VPU, GPU

Automotive with GPU, no VPU

Temperature Tj

Extended commercial: -20 to +105°CE

Industrial: -40 to +105°CC

Automotive: -40 to +125°CA

Frequency

800 MHz2 (Industrial grade)

852 MHz (Automotive grade)

1 GHz3

1.2 GHz

Package type

RoHS

FCPBGA 21x21 0.8mm (lidded)

FCPBGA 21x21 0.8mm (non lidded)

Qualification level

Prototype Samples

Mass Production

Special

Part # series

i.MX 6Quad

i.MX 6Dual

Silicon revision1

Rev 1.2

Rev 1.3

Rev 1.6

Fusing

Default setting

HDCP enabled

IMX6

1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.

2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.

3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.

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