AS3820 datasheet(26/52 Pages) DIALOG

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AS3820

16-Channel White LED Controller for LCD Backlight

Rev. 1.1

Datasheet

www.dialog-semiconductor.com

26 of 52

05-Feb-2019

8.3 Registers in PWM Generators

RegAddr: 0x13

PWM_CTRL

PLL_per_sel

DPLL frequency generation

0...DPLL-period = Vsync*PWMperiod

1...DPLL-period = Vsync*PLLmulti

ClockSrc1

Clock source for internal PWM-generators

0…Internal RC oscillator or HSYNC (depending on

ClockSrc0)

1...PLL output

Pwm_rev

0...Normal PWM operation

1...PWM signals are inverted

VSYNCdet

RW _AS

Enable VSYNC detection

0...VSYNC-detection OFF

1... VSYNC-detection ON. All current outputs are

turned OFF if VSYNC signal is missing for 100ms

VSYNCedge

Defines VSYNC trigger edge

0...VSYNC trigger on rising edge

1...VSYNC trigger on falling edge

Direct_PWM

RW _AS

Select external or internal PWM signal

0...PWM signal is generated internally

1...PWM signal is applied externally at pin VSYNC

Factory trim bit is read during startup. See section

Direct PWM Mode

Update_Mode

Defines when internal registers are updated

0...Registers updated with rising edge of xCS

1...Registers updated with next VSYNC-edge

ClockSrc0

Clock source for internal PWM-generators

0…Internal RC oscillator

1...External Pin HSYNC

See Note 1

Note 1. This bit only takes effect when ClockSrc1 = 0.

Table 24: PWM_CTRL

RegAddr: 0x15

RegAddr: 0x14

PWMperiod

Bit

Default

Access

Bit Description

4:0

7:0

0x00, 0x00

PWMper[12:0] sets PWM period

Table 25: PWMperiod

RegAddr: 0x17

RegAddr: 0x16

PWM1delay

Bit

Default

Access

Bit Description

3:0

7:0

0x00, 0x00

PWM1per[11:0] sets PWM1 delay

Table 26: PWM1delay

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