AT25SF641B datasheet(39/59 Pages) DIALOG

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AT25SF641B

DS-AT25SF641B–191D–12-2020

11.1.3 WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0”

state, the device does not accept any Byte/Page Program, erase, Program Security Register, Erase Security

or reset operation. Also, the WEL bit is reset to the logical “0” state automatically under the following conditions:

•

Write Disable operation completes successfully

•

Write Status Register operation completes successfully or aborts

•

Program Security Register operation completes successfully or aborts

•

Erase Security Register operation completes successfully or aborts

•

Byte/Page Program operation completes successfully or aborts

•

Block Erase operation completes successfully or aborts

•

Chip Erase operation completes successfully or aborts

If the WEL bit is in the logical “1” state, it is not reset to a logical “0” if an operation aborts due to an incomplete or

unrecognized opcode being clocked into the device before the CS pin is deasserted. For the WEL bit to be reset

when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program Security

11.1.4 RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in

progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data

must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a

logical “0”.

11.1.5 LB3, LB2, LB1 Bits

The LB3, LB2, and LB1 bits are used to determine if any of the three Security Register pages are locked.

The LB3 bit is in the logical “1” state if Security Register page-2 is locked and cannot be erased or programmed.

The LB2 bit is in the logical “1” state if Security Register page-1 is locked and cannot be erased or programmed.

The LB1 bit is in the logical “1” state if Security Register page-0 is locked and cannot be erased or programmed.

11.1.6 E_SUS Bit

This bit is set and cleared by hardware and indicates the status of an erase operation. This bit is encoded as

follows:

0: Erase operation is not suspended (default)

1: Erase operation is suspended

Hardware clears this bit once the condition that caused the erase suspend operation has been removed. Hardware

typically sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit when a

Program/Erase Resume (7Ah) command is executed.

11.1.7 P_SUS Bit

This bit is set and cleared by hardware and indicates the status of an program operation. This bit is encoded as

follows:

0: Program operation is not suspended (default)

1: Program operation is suspended

Hardware clears this bit once the condition that caused the program suspend operation has been removed.

Hardware typically sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit

when a Program/Erase Resume (7Ah) command is executed.

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