Access to the digital outputs is provided through con-

nector J1. The 40-pin connector easily interfaces with a

user-provided logic analyzer or data-acquisition system.

The DAV buffered output clock signal is available at pin

3 of J1 (CLKO) and is used to synchronize the output

data to the logic analyzer.

Power Supplies

The EV kits require separate analog and digital power

supplies for best performance. Separate 3.3V power

supplies are used to power the analog circuit blocks of

the converter (VDUT) and the clock-shaping circuit

(VCLK). To evaluate single-ended clock-signal opera-

tion, 3.3V must be supplied to VCLK. Separate 1.8V

power supplies are used to power the digital circuit

block of the converter (VLDUT) and the buffer/driver, U2

(VL). The digital circuit blocks of the EV kits operate with

voltage supplies as low as 1.7V and as high as 3.6V.

Clock Input

The MAX12553, MAX12554, and MAX12555 accept dif-

ferential or single-ended clock input signals. However,

the EV kits only accept a single-ended clock signal.

The EV kits include circuitry that converts a single-

ended signal to a differential clock signal through a

transformer or a user-installed differential clock driver

IC (U5). The EV kits also include clock-shaping circuitry

for a single-ended clock-signal configuration. Jumper

JU5 must be configured for differential or single-ended

clock-signal operation. See Table 1 for jumper settings.

Transformer-Coupled Differential Clock

A single-ended signal connected to the CLOCK SMA

connector is converted to a differential signal by trans-

former T3. In this mode, diode D1 limits the clock-signal

amplitude. Using this diode in the signal path allows the

clock signal to be increased significantly without violat-

ing the absolute maximum ratings of the converter

inputs, as the diode clips the input signal. Overdriving

the clock input to the board (CLOCK SMA) results in an

increased slew rate, which, in turn, compensates for the

negative effects that clock jitter imposes on parameters

such as signal-to-noise ratio (SNR) and signal-to-noise

plus distortion (SINAD). See Table 2 for jumper settings.

Install a shunt across pins 1-2 of jumper JU5 for differ-

ential clock operation. Note: While in transformer-

coupled differential clock mode, power to VCLK

should not be applied unless R10 is turned to one

extreme to avoid unnecessary triggering of U6.

Unnecessary triggering could potentially disturb the

ground plane with unwanted spur energy.

Clock-Shaping Circuit with Variable Duty Cycle

An on-board variable duty-cycle, clock-shaping circuit

generates a single-ended clock signal from an AC-cou-

pled sine wave applied to the CLOCK SMA connector.

Measure the clock signal at pin 2 of jumper JU7 and

adjust potentiometer R10 to obtain the desired duty

cycle. See Table 2 for shunt positions. A 3.3V voltage

source must be connected across VCLK and GND to

power the clock-circuit comparators.

Input Signal

The MAX12553, MAX12554, and MAX12555 accept dif-

ferential or single-ended analog input signals. However,

the EV kits require only a single-ended analog input

signal. Because the amplitude of the received signal at

the ADC depends on the actual cable and bandpass

filter loss, account for these losses when configuring

the signal-input generator. In differential mode, on-

board transformers T1 and T2 take the single-ended

analog input connected to the AINP SMA connector

and generate a differential analog signal at the ADC’s

input pins. For direct single-ended or differential input-

signal operation, the EV kit board circuit modifications

are listed in the

Direct AC-Coupled Differential Input

and

Direct AC-Coupled Single-Ended Input sections.

MAX12553/MAX12554/MAX12555

Evaluation Kits

4

_______________________________________________________________________________________

SHUNT

POSITION

CLKTYP PIN

CLOCK INPUT

CONFIGURATION

1-2*

Connected to VLDUT

Differential

2-3

Connected to GND

Single-Ended

Table 1. Clock Input Settings (JU5)

*

Default position.

JUMPER

SHUNT

POSITION

CLOCK MODE

JU4

2-3

JU6

1-2

JU7

2-3

JU8

2-3

Single-Ended Clock

Mode—See the Clock-Shaping

Circuit with Variable Duty Cycle

section.

JU4

1-2*

JU6

2-3*

JU7

1-2*

JU8

1-2*

Differential Clock Mode—A

single-ended signal is converted

to a differential signal that drives

the ADC clock inputs.

Table 2. Clock Drive Settings

*

Default position.