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ZL30264 Datasheet(PDF) 32 Page - Microchip Technology |
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ZL30264 Datasheet(HTML) 32 Page - Microchip Technology |
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32 / 93 page  ZL30264-ZL30267 Data Sheet 32 © 2021 Microchip Technology Inc. DS20006555A An exception for AFBDIV happens when AFBDL.RDCUR=1. In this case reads come directly from the internal logic and don’t affect the transfer register. Writes behave the same as above. A similar exception exists for A2FBDIV when A2FBDL.RDCUR=1. The multiregister fields are: Field Registers Type APLL1 AFBDIV[41:0] AFBDIV1 to AFBDIV6 Read/Write APLL2 AFBDIV[41:0] A2FBDIV1 to A2FBDIV6 Read/Write APLL1 FDIV[39:0] F1DIV1 to F1DIV5 Read/Write APLL2 FDIV[39:0] F2DIV1 to F2DIV5 Read/Write 6.1.4 Bank-Switched Registers (ZL30265 and ZL30267 Only) The EESEL register is a bank-select control field that maps the device registers into the memory map at address 0x1 and above when the EESEL bit is 0 and maps the EEPROM memory into the memory map at address 0x1 and above when the EESEL bit is 1. The EESEL register itself is always in the memory map at address 0x0. 6.2 Register Map Table 4 - Register Map ADDR REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Global Configuration Registers 00h EESEL EESEL — — — — — — — 01 MCR1 SRST HRST STOP — ROSCD AINCDIS ODMISO — 02 MCR2 XAMCK IC3MCK IC2MCK IC1MCK — DBL XAB[1:0] 03 PLLEN — — — — — — APLL2EN APLL1EN 04 ICEN — — — — — IC3EN IC2EN IC1EN 05 OCEN1 OC8EN OC7EN OC6EN OC5EN OC4EN OC3EN OC2EN OC1EN 06 OCEN2 — — — — — — OC10EN OC9EN 07 OCMUX1 — — OCMUXC[1:0] OCMUXB[1:0] OCMUXA[1:0] 08 OCMUX2 — — OCMUXF[1:0] OCMUXE[1:0] OCMUXD[1:0] 09 STOPCR1 OC8 OC7 OC6 OC5 OC4 OC3 OC2 OC1 0A STOPCR2 — — — — — — OC10 OC9 0B GPIOCR1 GPIO1C[3:0] GPIO0C[3:0] 0C GPIOCR2 GPIO3C[3:0] GPIO2C[3:0] 0D GPIO0SS REG[4:0] BIT[2:0] 0E GPIO1SS REG[4:0] BIT[2:0] 0F GPIO2SS REG[4:0] BIT[2:0] 10 GPIO3SS REG[4:0] BIT[2:0] 11 I2CA — I2CA[6:0] Status Registers 30 ID1 IDU[7:0] 31 ID2 IDL[3:0] REV[3:0] 40 CFGSR CFGD — IF[1:0] TEST AC[2:0] 41 GPIOSR GPIO3L GPIO2L GPIO1L GPIO0L GPIO3 GPIO2 GPIO1 GPIO0 42 INTSR — — OC IC — APLL INTIE INT 43 GLOBISR BCDONE — — — GPIO3IE GPIO2IE GPIO1IE GPIO0IE 44 ICISR — — — — XA IC3 IC2 IC1 45 OCISR1 OC8 OC7 OC6 OC5 OC4 OC3 OC2 OC1 46 OCISR2 — — — — — — OC10 OC9 |
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