ZL30264 datasheet(90/93 Pages) MICROCHIP

90 / 93 page

ZL30264-ZL30267

Data Sheet

DS20006555A

10. Acronyms and Abbreviations

APLL

analog phase locked loop

CML

current mode logic

GbE

gigabit Ethernet

HCSL

high-speed current steering logic

HSTL

high-speed transceiver logic

I/O

input/output

LOS

loss of signal

LVDS

low-voltage differential signal

LVPECL

low-voltage positive emitter-coupled logic

PFD

phase/frequency detector

PLL

phase locked loop

ppb

parts per billion

ppm

parts per million

pk-pk

peak-to-peak

RMS

root-mean-square

read-only

R/W

read/write

SS or SSM

spread spectrum modulation

TCXO

temperature-compensated crystal oscillator

unit interval

UIPP or UIP-P

unit interval, peak to peak

crystal oscillator

11. Data Sheet Revision History

Revision

Description

26-Sep-2016

First general release

08-Dec-2016

On page 1 added PCIe bullet.

In Table 1, OCx pin description, clarified what is programmable for each mode.

Added new Figure 17.

In Table 15 added max Input-to-Output Delay Variation numbers for external feedback using

on-die paths.

In Table 17 added min, typ and max values for buffer Input-to-Output Propagation Delay. In

footnotes 3 and 4 added “Measured at 125MHz”.

In Figure 17 added CMOS diagram.

12-Jun-2017

In section 2.4 and section 5.5.6.2 added note that NCO resolution of 1ppt is possible.

Corrected references to MCR1.XAB to MCR2.XAB.

Corrected four occurrences of VCCOx to VDDOx.

Added pullup recommendations to SCL/SCLK and SDA/MOSI pin descriptions.

Change ID2

.REV default value to “contact factory”.

In OCxCR2

.OCSF HCSL decode, deleted “VCM and VOD are ignored”.

17-Jul-2017

In Figure 17 removed the 50ohm to ground termination option from the CMOS diagram.

05-Sep-2017

In Table 1

TEST/GPIO3 pin description, changed “TEST must be low on the rising edge of

RSTN” to “Typically TEST should be low on the rising edge of RSTN, but see section 5.2 for

some options.”

In section 5.6.2 added the statement that maximum input frequency to the medium-speed

divider is 750MHz.

In section 5.6.5 clarified that signals from the same IntDiv or FracDiv are aligned and that

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