AM79C978AVCW datasheet(158/256 Pages) AMD

158 / 256 page

158

Am79C978A

accesses to these locations may

change the Am79C978A register

contents, but the EEPROM loca-

tions

will

not

affected.

EEPROM locations may be ac-

cessed directly through BCR19.

At the end of the read operation,

the PREAD bit will automatically be

reset to a 0 by the Am79C978A

controller and PVALID will be set,

provided that an EEPROM existed

on the interface pins and that the

checksum for the entire 68 bytes of

EEPROM was correct.

Note that when PREAD is set to a

1, then the Am79C978A control-

ler will no longer respond to any

accesses directed toward it, until

the PREAD operation has com-

pleted successfully. The control-

ler will terminate these accesses

with the assertion of DEVSEL

and STOP while TRDY is not as-

serted, signaling to the initiator to

disconnect and retry the access

at a later time.

If a PREAD command is given to

the Am79C978A controller but no

EEPROM is attached to the inter-

face pins, the PREAD bit will be

cleared to a 0, and the PVALID bit

will remain reset with a value of 0.

This applies to the automatic read

of the EEPROM after H_RESET

as well as to host initiated PREAD

commands. EEPROM program-

mable locations on board the

Am79C978A controller will be set

to their default values by such an

aborted PREAD operation. For ex-

ample, if the aborted PREAD oper-

ation immediately followed the

H_RESET operation, then the final

state of the EEPROM programma-

ble locations will be equal to the

H_RESET programming for those

locations.

If a PREAD command is given

to the Am79C978A controller

and

the

auto-detection

(EESK/LED1) indicates that no

EEPROM is present, then the

EEPROM read operation will

still be attempted.

Note that at the end of the

H_RESET operation, a read of

the EEPROM will be performed

automatically. This H_RESET-

generated EEPROM read func-

tion will not proceed if the auto-

detection pin (EESK/LED1) indi-

cates

that

EEPROM

present.

This bit is read accessible al-

ways; write accessible only when

either the STOP or the SPND bit

is set. PREAD is set to 0 during

H_RESET and is unaffected by

S_RESET or the STOP bit.

EEDET

EEPROM Detect. This bit indi-

cates the sampled value of the

EESK/LED1 pin at the end of

H_RESET. This value indicates

whether or not an EEPROM is

present at the EEPROM inter-

face. If this bit is a 1, it indicates

that an EEPROM is present. If

this bit is a 0, it indicates that an

EEPROM is not present.

This bit is read accessible only.

EEDET is read only; write opera-

tions have no effect. The value of

this bit is determined at the end of

the H_RESET operation. It is un-

affected by S_RESET or the

STOP bit.

Table 39 indicates the possible

combinations of EEDET and the

existence of an EEPROM and the

resulting operations that are pos-

sible on the EEPROM interface.

12-5

RES

Reserved locations. Written as

zeros; read as undefined.

EEN

EEPROM Port Enable. When this

bit is set to a 1, it causes the val-

ues of ECS, ESK, and EDI to be

driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN = 0 and no EEPROM read

function is currently active, then

EECS will be driven LOW. When

EEN = 0 and no EEPROM read

function is currently active, EESK

and EEDI pins will be driven by

the LED registers BCR5 and

BCR4, respectively. See Table

40.

AM79C978AVCW Datasheet(PDF) 158 Page - Advanced Micro Devices

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