AM79C978AVCW datasheet(156/256 Pages) AMD

156 / 256 page

156

Am79C978A

This bit is read accessible al-

ways, write accessible only when

either the STOP or the SPND bit

is set. EXTREQ is cleared by

H_RESET and is not affected by

S_RESET or STOP.

DWIO

Double Word I/O. When set, this

bit indicates that the Am79C978A

controller

programmed

for

DWord I/O (DWIO) mode. When

cleared, this bit indicates that the

Am79C978A controller is pro-

grammed for Word I/O (WIO)

mode. This bit affects the I/O Re-

source Offset map and it affects

the

defined

width

the

Am79C978A controller’s I/O re-

sources. See the DWIO and WIO

sections for more details.

The initial value of the DWIO bit is

determined by the programming

of the EEPROM.

The value of DWIO can be al-

tered

automatically

the

Am79C978A controller. Specifi-

cally, the Am79C978A controller

will set DWIO if it detects a

DWord write access to offset 10h

from the Am79C978A controller’s

I/O base address (corresponding

to the RDP resource).

Once the DWIO bit has been set

to a 1, only a H_RESET or an EE-

PROM read can reset it to a 0.

(Note that the EEPROM read op-

eration will only set DWIO to a 0 if

the appropriate bit inside of the

EEPROM is set to 0.)

This bit is read accessible al-

ways. DWIO is read only, write

operations have no effect. DWIO

is cleared by H_RESET and is

not affected S_RESET or by set-

ting the STOP bit.

BREAD E

B u r st Re ad En able . Whe n

se t, th is b i t ena ble s bu r s t

mo de du r ing mem o r y r e a d

a ccesses.

Whe n

cle a red ,

t h is bit pr eve n ts t he de vice

f r om

pe r f or m i ng

bu r s tin g

d u ring rea d accesse s. T h e

Am 79C 978 A cont r o lle r ca n

pe r f o r m

bu r s t

t r ansf e r s

w hen r e a d in g t he init iali za-

t i on b l ock, th e de scr ipt o r

r i n g

en tr ie s

( w he n

SWSTYL E = 3),

and

th e

bu ff er mem o r y .

BREADE should be set to 1

when the Am79C978A control-

ler is used in a PCI bus applica-

tion

guarantee

maximum

performance.

This bit is read accessible al-

ways; write accessible only when

either the STOP or the SPND bit

is set. BREADE is cleared by

H_RESET and is not affected by

S_RESET or STOP.

BWRITE

Burst Write Enable. When set,

this bit enables burst mode during

memory write accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during

write

accesses.

The

Am79C978A controller can per-

form burst transfers when writing

the descriptor ring entries (when

SWSTYLE = 3), and the buffer

memory.

BWRITE should be set to 1

when the Am79C978A control-

ler is used in a PCI bus applica-

tion

guarantee

maximum

performance.

This bit is read accessible al-

ways, write accessible only when

either the STOP or the SPND bit

is set. BWRITE is cleared by

H_RESET and is not affected by

S_RESET or STOP.

4-3

PHYSEL[1:0] PHYSEL[1:0] bits allow for soft-

ware controlled selection of differ-

ent operation and test modes. The

normal mode of operation is when

both bits 0 and 1 are set to 0 to se-

lect the Expansion ROM/Flash.

Setting bit 0 to 1 and bit 1 to 0 al-

lows snooping of the internal MII-

compatible bus to allow External

Address

Detection

Interface

(EADI). See Table 38 for details.

AM79C978AVCW Datasheet(PDF) 156 Page - Advanced Micro Devices

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