AM79C978AVCW datasheet(153/256 Pages) AMD

153 / 256 page

Am79C978A

153

by S_RESET or setting the

STOP bit.

RCVME

Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

This bit is always read/write ac-

cessible. RCVME is cleared by

H_RESET and is not affected

by S_RESET or setting the

STOP bit.

XMTE

Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. XMTE is set to 1 by

H_RESET and is not affected

by S_RESET or setting the

STOP bit.

POWER

Power. When this bit is set to 1,

the device is operating in HIGH

power mode.

RCVE

Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. RCVE is cleared by

H_RESET and is not affected

by S_RESET or setting the

STOP bit.

SPEED

Speed. When this bit is set to 1,

the device is operating in HIGH

speed mode.

COLE

Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

This bit is always read/write ac-

cessible. COLE is cleared by

H_RESET and is not affected

by S_RESET or setting the

STOP bit.

BCR9: Full-Duplex Control

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-3

RES

Reserved locations. Written as

zeros and read as undefined.

FDRPAD

Full-Duplex Runt Packet Accept

Disable. When FDRPAD is set to

1 and full-duplex mode is en-

abled, the Am79C978A controller

will only receive frames that meet

the

minimum

Ethernet

frame

length of 64 bytes. Receive DMA

will not start until at least 64 bytes

or a complete frame have been

received. By default, FDRPAD is

cleared to 0. The Am79C978A

controller will accept any length

frame and receive DMA will start

according to the programming of

the

receive

FIFO

watermark.

Note that there should not be any

runt packets in a full-duplex net-

work, since the main cause for

runt packets is a network collision

and there are no collisions in a

full-duplex network.

This bit is always read/write ac-

cessible. FDRPAD is cleared

by H_RESET and is not affect-

ed by S_RESET or by setting

the STOP bit.

RES

Reserved locations. Written as

zeros and read as undefined.

FDEN

Full-Duplex Enable. FDEN con-

trols whether full-duplex opera-

tion is enabled. When FDEN is

cleared and the Auto-Negotiation

is disabled, full-duplex operation

not

enabled

and

the

Am79C978A controller will al-

ways

operate

half-duplex

mode. When FDEN is set, the

Am79C978A controller will oper-

ate in full-duplex mode.

AM79C978AVCW Datasheet(PDF) 153 Page - Advanced Micro Devices

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