V3025 datasheet(14/17 Pages) EMMICRO

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V3025

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IRQ

The IRQ output is used by 4 of the V3025's features.

These are:

1. Pulse,

provide

periodic

interrupts

the

microprocessors at pre-programmed intervals;

2. Alarm to provide an interrupt to the microprocessor at

a pre-programmed time and date;

3. Timer, to provide an interrupt to the microprocessor

when the time rolls over from 23:59:59:99 to

00:00:00:00; and

4. Frequency

trimming

(see

section

"Frequency

Trimming").

The first 3 features listed are similar in the way they

provide interrupts to the microprocessor. Each of the 3

has an enable / disable bit, a flag bit, and an interrupt

mask bit. The enable / disable bit allows software to

select a feature or not. A set flag bit indicates that an

enable feature has reached its interrupt condition.

Software must clear the flag bit. The interrupt mask bit

allows or disallows the IRQ output to become active

when the flag bit is se. The IRQ output becomes active

whenever any interrupt flag is set which also has its mask

bit set. For all sources of maskable interrupts within the

V3025, the IRQ output will remain active until software

clears the interrupt flag. The IRQ output is the logical OR

of all the unmasked interrupt flags. The IRQ output is

open drain so an external pullup to VDD is needed. In

standby ( PF active) the IRQ output will be active if the

alarm mask bit (addr, 01 hex, bit 1) is set and the alarm

flag is also set. The timer or the pulse feature cannot

cause the IRQ output to become active while in standby.

Snychronization

There are 3 ways to synchronize the V3025. It can be

synchronized to 50 Hz, the nearest second, or the nearest

minute. Synchronization mode is selected by setting one

of the bits 5 to 7 at addr. 02 hex, in accordance with Table

8. If more than one bit is set then all the synchronization

bits are disabled. If the SYNC input is set low for longer

than 200 µs, while in the synchronization mode, the clock

will synchronize to the falling edge of the signal.

Synchronization to the nearest second implies that the

1/100 seconds are cleared to zero and if the contents

were > 50, the seconds register is incremented.

Synchronization to the nearest minute implies that the

seconds are cleared to zero and if the contents were > 30,

the minutes register is incremented. Fractions of seconds

are cleared.

Pulse

There are 4 programmable pulse frequencies available on

the V3025, these are every 10 ms, 100 ms, second or

minute. The pulse feature is activated by setting the pulse

enable / disable bit at address 00, bit 1.

The pulse

frequency is selected by setting one of the bit 0 to 3 at

address 02 hex (see Table 9). If more than one of the

pulse bits is set then the feature is disabled.

At the

selected interval the pulse flag bit (addr. 01 hex, bit 4) is

set. If the pulse mask bit (addr. 01 hex, bit 0) is set then

the IRQ pin goes active. The pulse flag indicates to

software the source of the interrupt.

IRQ

will remain

active until software acknowledges the interrupt by

clearing the pulse flag. The pulse feature is disabled

while in standby.

Upon power restoration the pulse

feature is enabled if enabled prior to standby. See also

the section "Frequency Tuning".

Note: The user should ensure that a time lapse of at least

60 microseconds exists between the falling edge of the

IRQ

and the clearing of the pulse flag.

Time Set Lock

The time set lock control bit is located at address 00 hex,

bit 5 (see Table 7).

When set by software, this bit

disables any transfer from the RAM to the reserved clock

and timer area as well as inhibiting any write to the digital

trimming register at address 10 hex. When the time set

lock bit is set the following transfer operations are

disabled:

The clock command followed by write,

the timer command followed by write,

the clock and timer command followed by write, and

writing to the digital trimming register

A set bit prevents unauthorized overwriting of the

reserved clock and timer area. Reading of the reserved

clock and timer area, using the commands, is not affected

by the time set lock bit. Clearing the time set lock bit by

software will re-enable the above listed commands. On

initialisation the time set lock bit is cleared. The time set

lock bit does not affect the user RAM (addr. 50 to 5F hex).

Frequency Tuning

The V3025 offers a key feature called "Digital Trimming",

which is used for the clock accuracy adjustment. Unlike

the traditional capacitor trimming method which tunes the

crystal oscillator, the digital trimming acts on the divider

chain, allowing the clock adjustment by software. The

oscillator frequency itself is not affected.

The Principle of Digital Trimming

With the digital trimming disabled (ie. digital trimming

the divider chain will run slightly too fast (typ. 210 ppm:

ppm = parts per million), and will generate a 100 Hz signal

with a frequency of typically 100.021 Hz. To correct this

frequency, the digital trimming logic will inhibit every 31

seconds, a number of clock pulses, as set in the digital

trimming register.

Since the duration of 31 seconds

corresponds to 1'015'808 oscillator cycles, the digital

trimming has a resolution of 0.984 ppm. In other words

every increment by 1 of the digital trimming value will slow

down the clock by 0.984 ppm, which permits the accuracy

of ± 0.5 ppm to be reached. Note that a 1 ppm error will

result in a 1 second difference after 11.5 days, or a 1

minute difference after 694 days ! The trimming range of

the V3025 is from 0 to 251 ppm. The 251 ppm correction

is obtained by writing 255 (FFhex) into the digital trimming

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