V3025 datasheet(2/17 Pages) EMMICRO

2 / 17 page

V3025

www.emmicroelectronic.com

Absolute Maximum Ratings

Parameter

Symbol

Conditions

Maximum voltage at VDD and

VBAT

VSUPmax

VSS + 7.0V

Max. voltage at remaining pins VSUP

VDD + 0.3V

Min. voltage on all pins

Vmin

VSS – 0.3V

Maximum storage temperature TSTOmax

+125°C

Minimum storage temperature TSTOmin

-55°C

Maximum electrostatic

discharge to MIL-STD-883C

method 3015.7 with ref. to VSS

VSmax

1000V

Maximum soldering conditions TSmax

250°C x 10s

Shock resistance

5000 g.

0.3ms, ½ sine

Table 1

Stresses above these listed maximum ratings may cause

permanent damages to the device. Exposure beyond

specified operating conditions may affect device reliability

or cause malfunction.

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, anti-static precautions

must be taken as for any other CMOS component. Unless

otherwise specified, proper operation can only occur when

all terminal voltages are kept within the voltage range.

Unused inputs must always be tied to a defined logic

voltage level.

Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Operating temperature

-40

+85

°C

Main supply voltage

VDD

5.5

Battery supply voltage

VBAT

Logic supply voltage

VSUP

2.0

5.0

5.5

Supply voltage dv/dt

(power-up & down)

dv/dt

V/µs

Decoupling capacitor

100

Table 2

Electrical Characteristics

VDD = 5.0V ±10%, VBAT = 3V, TA = -40 to +85°C, unless otherwise specified

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Standby current (note 1)

IDD1

VDD = 3 V, VBAT = 0V, PFI = 0

1.2

µA

IDD2

VDD = 5.5 V, PFI = 0

2.5

µA

Standby current (note 1)

IBAT

VDD = 0 V, PFI = 0

1.3

µA

Dynamic current (note 2)

IDYN

= 4 MHz, RD = VSS

= VDD

1.5

IRQ

(open drain)

Output low voltage

VOL

IOL = 6 mA

0.4

Output low voltage

VOL

IOL = 1 mA, VDD = 2 V

0.4

Inputs and Outputs

Input logic low

VIL

TA = +25°C

0.2 VSUP

Input logic high

VIH

TA = +25°C

0.8 VSUP

Output logic low

VOL

IOL = 6 mA

0.4

Output logic high

VOH

IOH = 6 mA

2.4

PFI

activation voltage

VPFL

0.5 VDD

PFI

hysteresis

TA = +25°C

100

Pullup on SYNC

ILS

VILS = 0.8 V

µA

Input leakage

IIN

VSS < VIN < VDD

1000

Output tri-state leakage

ITS

= 1

1000

Oscillator Characteristics

Starting voltage

VSTA

TA ≥ +25°C

VSTA

2.5

Frequency Characteristics

Start-up time

TSTA

Frequency tolerance

∆f/f

TA = +25°C addr. 10 hex = 00

hex

150

210

(note 4)

251

ppm

Frequency stability

fsta

2.0 ≤ VDD ≤ 5.5 V (note 3)

ppm/V

Temperature stability

tsta

addr. 10 hex = 00 hex

see Fig.6

ppm

Aging

tag

TA = +25°C, first year

±5

ppm/year

Accuracy versus switch-

over

ASW

VBAT = 3V, 10 pulses of VDD

switching between 2 to 5V in

70ms

0.2

ppm

Table 3

Note 1

: With PFO = 0 (VSS) all I/O pads can be tri-state, tested.

With PFO = 1 (VSUP), CS = 1 (VDD) and all other I/O pads fixed to VSUP or VSS: same standby current, not tested.

Note 2

: All other inputs to VDD and all outputs open.

Note 3

: At a given temperature.

Note 4

: See Fig. 5

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