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IMX6SDLIEC Datasheet(PDF) 110 Page - NXP Semiconductors |
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IMX6SDLIEC Datasheet(HTML) 110 Page - NXP Semiconductors |
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110 / 161 page ![]() i.MX 6Solo/6DualLite Applications Processors for Industrial Products, Rev. 9, 11/2018 110 NXP Semiconductors Electrical Characteristics 4.11.13.5 Stream Transmission Mode Frame Transfer Figure 76. Stream Transmission Mode Frame Transfer (Synchronized Data Flow) 4.11.13.6 Frame Transmission Mode (Synchronized Data Flow) Figure 77. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow) 4.11.13.7 Frame Transmission Mode (Pipelined Data Flow) Figure 78. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow) 4.11.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load Table 68. DATA and FLAG Timing Parameter Description 1 Mbit/s 100 Mbit/s 200 Mbit/s tBit, nom Nominal bit time 1000 ns 10.0 ns 5.00 ns tRise, min and tFall, min Minimum allowed rise and fall time 2.00 ns 2.00 ns 1.00 ns tTxToRxSkew, maxfq Maximum skew between transmitter and receiver package pins 50.0 ns 0.5.0 ns 0.25 ns |
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