IMX6SDLIEC datasheet(111/161 Pages) NXP

111 / 161 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Industrial Products, Rev. 9, 11/2018

NXP Semiconductors

111

Figure 79. DATA and FLAG Signal Timing

4.11.14 PCIe PHY Parameters

The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0

standard.

4.11.14.1 PCIE_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 200

Ω. 1% precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.11.15 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

tEageSepTx, min

Minimum allowed separation of signal transitions at transmitter

package pins, including all timing defects, for example, jitter

and skew, inside the transmitter.

400 ns

4.00 ns

2.00 ns

tEageSepRx, min

Minimum separation of signal transitions, measured at the

receiver package pins, including all timing defects, for example,

jitter and skew, inside the receiver.

350 ns

3.5 ns

1.75 ns

Table 68. DATA and FLAG Timing (continued)

Parameter

Description

1 Mbit/s

100 Mbit/s

200 Mbit/s

1 This case shows that the DATA signal has slowed down more compared to the FLAG signal

2 This case shows that the FLAG signal has slowed down more compared to the DATA signal.

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