Electronic Components Datasheet Search
  English  ▼

X  

MPC7457 Datasheet(PDF) 3 Page - NXP Semiconductors

Part # MPC7457
Description  MPC7457 Hardware Specification Addendum for the MPC74n7RXnnnnNx Series
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC7457 Datasheet(HTML) 3 Page - NXP Semiconductors

  MPC7457 Datasheet HTML 1Page - NXP Semiconductors MPC7457 Datasheet HTML 2Page - NXP Semiconductors MPC7457 Datasheet HTML 3Page - NXP Semiconductors MPC7457 Datasheet HTML 4Page - NXP Semiconductors MPC7457 Datasheet HTML 5Page - NXP Semiconductors MPC7457 Datasheet HTML 6Page - NXP Semiconductors MPC7457 Datasheet HTML 7Page - NXP Semiconductors MPC7457 Datasheet HTML 8Page - NXP Semiconductors MPC7457 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 12 page
background image
MPC7457 Hardware Specification Addendum for the MPC74n7RXnnnnNx Series, Rev. 3
Freescale Semiconductor
3
General Parameters
Table 7 provides the power consumption for the MPC7457 part numbers described herein.
Table 7. Power Consumption for MPC7457
Processor (CPU) Frequency
Unit
Notes
600 MHz
733 MHz
867 MHz
1000 MHz
Full-Power Mode
Typical
5.3
6.3
7.3
8.3
W
1, 3
Maximum
7.9
9.1
10.3
11.5
W
1, 2
Doze Mode
Typical
—
———
W
4
Nap Mode
Typical
1.3
1.3
1.3
1.3
W
1, 2
Sleep Mode
Typical
1.2
1.2
1.2
1.2
W
1, 2
Deep Sleep Mode (PLL Disabled)
Typical
1.1
1.1
1.1
1.1
W
1, 3
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD
and GVDD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD
power. Worst case power consumption for AVDD < 3 mW.
2. Maximum power is the maximum measured at nominal VDD and maximum operating junction temperature (see Table 4)
while running an entirely cache-resident, contrived sequence of instructions which keep all the execution units
maximally busy.
3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while running
the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode.
As a result, power consumption for this mode is not tested.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com