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MPC7457 Datasheet(PDF) 4 Page - NXP Semiconductors

Part # MPC7457
Description  MPC7457 Hardware Specification Addendum for the MPC74n7RXnnnnNx Series
PDF  12 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC7457 Datasheet(HTML) 4 Page - NXP Semiconductors

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MPC7457 Hardware Specification Addendum for the MPC74n7RXnnnnNx Series, Rev. 3
4
Freescale Semiconductor
General Parameters
Table 8 provides the clock AC timing specifications for the MPC7457 part numbers described herein.
5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7457 part numbers described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
600 MHz
733 MHz
867 MHz
1000 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
500
600
500
733
500
867
500
1000
MHz
1
VCO frequency
fVCO
1000
1200
1000
1466
1000
1733
1000
2000
MHz
1
SYSCLK frequency
fSYSCLK
33
167
33
167
33
167
33
167
MHz
1, 2
SYSCLK cycle time
tSYSCLK
6.0
30
6.0
30
6.0
30
6.0
30
ns
2
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in
MPC7457 RISC Microprocessor
Hardware Specifications, Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4] settings.
2. Assumes lightly-loaded, single-processor system; see
MPC7457 RISC Microprocessor Hardware Specifications,
Section 5.2.1, “Clock AC Specifications” for more information.
Table 9. Processor Bus AC Timing Specifications 1
At recommended operating conditions. See Table 4.
Parameter
Symbol 2
All Speed Grades
Unit
Notes
Min
Max
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1],
BMODE[0:1], BVSEL, L3VSEL
tAVKH
tDVKH
tIVKH
tMVKH
2.0
2.0
2.0
2.0
—
—
—
—
ns
8
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
tAXKH
tDXKH
tIXKH
tMXKH
0
0
0
0
—
—
—
—
ns
8
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,
PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], TS, SHD[0:1],
WT
tKHAV
tKHDV
tKHOV
—
—
—
2.0
2.0
2.0
ns



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