81006AK

www.icst.com/products/hiperclocks.html

REV. A JANUARY 4, 2006

10

Integrated

Circuit

Systems, Inc.

ICS81006

l

o

b

m

y

Sr

e

t

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m

a

r

a

Ps

n

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i

t

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d

n

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t

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u

m

i

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y

Tm

u

m

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t

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c

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p

a

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r

o

t

c

a

r

a

V

w

o

LV

C

V

0

=4

.

5

1F

p

C

H

G

I

H

_

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e

c

n

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a

p

a

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r

o

t

c

a

r

a

V

h

g

i

HV

C

V

3

.

3

=6

.

9

2F

p

(

) (

)

() (

)

Low

V

S

L

Low

V

S

L

Low

V

S

L

Low

V

S

L

Low

C

C

C

C

C

C

C

C

C

C

C

C

C

_

2

2

_

1

1

_

2

2

_

1

1

+

+

+

+

+

+

+

⋅

+

+

=

(

) (

)

() (

)

High

V

S

L

High

V

S

L

High

V

S

L

High

V

S

L

High

C

C

C

C

C

C

C

C

C

C

C

C

C

_

2

2

_

1

1

_

2

2

_

1

1

+

+

+

+

+

+

+

⋅

+

+

=

6

0

1

0

0

1

0

10

1

2

1

1

2

1

)

(

⋅

⎟

⎟

⎟

⎟

⎠

⎞

⎜

⎜

⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛ +

⋅

⋅

−

⎟

⎠

⎞

⎜

⎝

⎛ +

⋅

⋅

=

C

C

C

C

C

C

C

C

TPR

Range

Pull

Total

High

Low

•C

C

•C

C

Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)

Using the tables and figures above, we can now calculate the

TPR and APR of the VCXO using the example crystal

parameters. For the numerical example below there were some

assumptions made. First, the stray capacitance (C

is all the excess capacitance due to board parasitic, is 4pF.

Second, the expected lifetime of the project is 5 years; hence

the inaccuracy due to aging is ±15ppm. Third, though many

boards will not require load tuning capacitors (C

recommended for long-term consistent performance of the

system that two tuning capacitor pads be placed into every

design. Typical values for the load tuning capacitors will range

from 0 to 4pF.

() ()

() ()

pf

pf

pf

pf

pf

pf

pf

pf

pf

C

Low

7

.

9

4

.

15

4

0

4

.

15

4

0

4

.

15

4

0

4

.

15

4

0

=

+

+

+

+

+

+

+

⋅

+

+

=

() ()

() (

)

pf

pf

pf

pf

pf

pf

pf

pf

pf

C

High

8

.

16

6

.

29

4

0

6

.

29

4

0

6

.

29

4

0

6

.

29

4

0

=

+

+

+

+

+

+

+

⋅

+

+

=

ppm

pF

pF

pF

pF

TPR

5

.

226

10

4

8

.

16

1

220

2

1

4

7

.

9

1

220

2

1

6

=

⋅

⋅

⎟⎟

⎟

⎟

⎠

⎞

⎜⎜

⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛ +

⋅

⋅

−

⎟

⎠

⎞

⎜

⎝

⎛ +

⋅

⋅

=

TPR = ±113.25ppm

APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm

The example above will ensure a total pull range of

±113.25 ppm with an APR of ±58.25ppm. Many times, board

designers may select their own crystal based on their

application. If the application requires a tighter APR, a crystal

with better pullability (C0/C1 ratio) can be used. Also, with the

equations above, one can vary the frequency tolerance,

temperature stability, and aging or shunt capacitance to achieve

the required pullability.