81006AK

www.icst.com/products/hiperclocks.html

REV. A JANUARY 4, 2006

11

Integrated

Circuit

Systems, Inc.

ICS81006

Figure 2 shows an example of ICS81006 application sche-

matic. The decoupling capacitors should be located as close

as possible to the power pin. For the LVCMOS 20

Ω output

drivers, series termination example is shown in the sche-

matic. Additional termination approaches are shown in the

LVCMOS Termination Application Note.

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used. The VC pin can not be

floated.

All unused LVCMOS output can be left floating. We

recommend that there is no trace attached.

C2

SPARE

R5

1K

VC = 0V to VDD

VDD

C1

SPARE

U1

81006

2

3

4

5

11

12

13

14

15

1

XTAL_OUT

VDD

VC

DIV_SEL_Q5

GND

Q3

VDDO

Q2

GND

XTAL_IN

Zo = 50

(U1-13)

C3

0.1uF

Unused outputs can be left floating. There should be

no trace attached to unused outputs. Device

characterized and specification limits set with all

outputs terminated.

C6

0.1uF

C5

0.1uF

C7

10uf

Pull-up

example

(U1-9)

R4

1K

Quartz crystal should be

placed as close to the

device as possible.

VDDO

Pull-down

example

VDD

R3

1K

VDDO

R1

30

VDD

R2

30

VC

C4

0.1uF

XTAL

(U1-17)

Zo = 50

VDD

(U1-3)