LTC5596 datasheet(17/22 Pages) AD

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LTC5597

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

The LTC5597 is a true RMS RF power detector, capable

of measuring an RF signal over the frequency range from

100MHz to 70GHz, independent of input waveforms with

differentcrestfactorssuchasCW,WCDMA,OFDM(LTEand

WiFi) signals. Up to 35dB dynamic range is achieved with

a very stable output within the full case temperature range.

RF Input

The single-ended RF input is internally matched to 50Ω,

both in active mode and the low power shutdown mode.

The DC voltage applied to this pin should be kept below

1V, to avoid damage to the internal circuitry, depicted in

Figure 3.

RFIN

5597 F03

LTC5597

50fF

125pH

Figure 3. Simplified Schematic of the RFIN Interface

Together with GND Pin 5 and Pin 7, RFIN (Pin 6) forms

a ground-signal-ground configuration that can interface

directly with a co-planar waveguide on the PCB. The rec-

ommended design is depicted in Figure 4.

To minimize reflections at high frequencies, the center

strip has been chosen the same width as the RFIN pack-

age pin (10mils).

The LTC5597 evaluation board uses a 5mils thick layer of

Rogers RO3003 material for the top substrate to achieve

low dielectric losses up to 70GHz. The other two sub-

strates on the board are regular FR-4 material. Using this

configuration,a50Ωcharacteristicimpedanceisobtained

for a 9mils gap width between the center strip and the

two ground return conductors. Vias connecting the top

ground conductors with the second metal ground plane

should be placed along the edge of the GCPW top ground

conductors. Via dimensions should be kept as small as

possible. The evaluation board uses vias with a diameter

of 6mils or 8mils including the metal edge ring (donut).

10mils

9mils

5mils

RO3003

VIA

5597 F04

Figure 4. Grounded Co-Planar Waveguide (GCPW) to Interface RFIN

FLTR Interface (Pin 3):

This pin enables additional suppression of high frequency

ripple in the detector output signal, at the expense of a

slower detector response (longer rise time, fall time and

propagation delay). As depicted in Figure 1, an external

capacitor C3 connected between FLTR and OUT enlarges

the amount of feedback capacitance across the output

amplifier, and reduces the output filter bandwidth with-

out affecting the current drive capability of the LTC5597.

Suitable capacitance values are in the range from 10pF

up to 1nF, but the total of feedback and load capacitance

(from OUT to signal ground) should not exceed 1nF.

Larger capacitance values may result in instability of the

output driver.

To avoid permanent damage to the chip, the DC voltage

at the FLTR pin should not exceed 0.4V. Similarly, it is not

recommended to supply a DC bias current to this pin in

excess of about 100μA.

OUT Interface (Pin 2):

The OUT interface, depicted in Figure 5, is a class-AB

CMOS output stage that can source and sink over 20mA

of load current.

It is able to drive a load resistance of 50Ω (or higher) over

the full output voltage range. Short-circuiting the OUT

interface should be avoided though, as this can lead to

permanentdamageofthedevice.Theoutputdriverisstable

for capacitive loads up to at least 1nF. This includes any

externalfeedbackcapacitancebetweenOUTandFLTR,which

is essentially experienced as a load by the driver amplifier.

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