PIN

NAME

FUNCTION

1–3

IN

Overvoltage-Protection Input. Bypass IN to GND with a 0.47FF ceramic capacitor placed as close

as possible to the device. Use a 0.47FF, low-ESR ceramic capacitor to enable Q15kV (HBM) ESD

protection on IN. For hot-plug applications, see the Applications Information section.

4

UVLO

Externally Programmable Undervoltage-Lockout Threshold. Connect UVLO to GND to use the

default internal UVLO threshold. Connect UVLO to an external resistor-divider to define a threshold

externally and override the preset internal UVLO threshold.

5

OVLO

Externally Programmable Overvoltage-Lockout Threshold. Connect OVLO to GND to use the

default internal OVLO threshold. Connect OVLO to an external resistor-divider to define a threshold

externally and override the preset internal OVLO threshold.

6

SETI

Overload Current-Limit Adjust. Connect a resistor from SETI to GND to program the overcurrent

limit. If SETI is unconnected, the current limit is set to 0A. If SETI is less than 1V (typ), the FETs

turn off and FLAG is asserted. Do not connect more than 10pF to SETI.

7

GND

Ground

8

HVEN

36V Capable Active-Low Enable Input. See Table 1.

9

RIEN

Reverse-Current Enable Input. Connect RIEN to GND to enable the reverse-current flow protection.

Connect RIEN to logic-high to disable the reverse-current flow protection.

10

EN

Active-High Enable Input. See Table 1.

11

FLAG

Open-Drain, Fault Indicator Output. FLAG goes low when the fault duration exceeds the blanking

time, reverse current is detected, thermal-shutdown mode is active, OVLO threshold is reached, or

SETI is connected to GND.

12, 13, 14

OUT

Output Voltage. Output of internal FETs. Bypass OUT to GND with a 1FF ceramic capacitor placed

as close as possible to the device. For a long output cable or inductive lead, see the Applications

Information section.

—

EP

Exposed Pad. Always connect EP to the GND pin of the IC. Also, connect EP to a large GND plane

with several thermal vias for best Thermal performance. Refer to the MAX17561 EV kit data sheet for

an example of the correct method for EP connection and thermal vias.

14

13

12

11

10

9

8

1

2

3

4

5

6

7

OUT

OUT

OUT

UVLO

IN

IN

IN

TOP VIEW

MAX17561

MAX17562

MAX17563

EN

RIEN

GND

SETI

OVLO

*EP

TSSOP

*CONNECT EXPOSED PAD TO GND

FLAG

HVEN

+

Pin Configuration

Pin Description

www.maximintegrated.com

Maxim Integrated │ 10

MAX17561/MAX17562/

MAX17563

Adjustable Overvoltage and Overcurrent

Protectors with High Accuracy