AT90USB646 datasheet(161/434 Pages) ATMEL

161 / 434 page

161

7593A–AVR–02/06

AT90USB64/128

Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O/8)

15.8 8-bit Timer/Counter Register Description

15.8.1

Timer/Counter Control Register A – TCCR2A

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 15-1 shows the COM2A1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

543

COM2A

COM2B

––

WGM2

TCCR2A

Read/Write

R/W

Initial Value

Table 15-1.

Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

Normal port operation, OC0A disconnected.

Toggle OC2A on Compare Match

Clear OC2A on Compare Match

Set OC2A on Compare Match

AT90USB646 Datasheet(PDF) 161 Page - ATMEL Corporation

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