AT90USB646 datasheet(270/434 Pages) ATMEL

270 / 434 page

270

7593A–AVR–02/06

AT90USB64/128

22.4 Endpoint reset

An endpoint can be reset at any time by setting in the UERST register the bit corresponding to

the endpoint (EPRSTx). This resets:

• the internal state machine on that endpoint,

• the Rx and Tx banks are cleared and their internal pointers are restored,

• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.

The data toggle field remains unchanged.

The other registers remain unchanged.

The endpoint configuration remains active and the endpoint is still enabled.

The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as

an answer to the CLEAR_FEATURE USB command.

22.5 USB reset

When an USB reset is detected on the USB line, the next operations are performed by the

controller:

• all the endpoints are disabled, except the default control endpoint,

• the default control endpoint is reset (see Section 22.4, page 270 for more details).

• The data toggle of the default control endpoint is cleared.

22.6 Endpoint selection

Prior to any operation performed by the CPU, the endpoint must first be selected. This is done

by:

• Clearing EPNUMS.

• Setting EPNUM with the endpoint number which will be managed by the CPU.

The CPU can then access to the various endpoint registers and data.

22.7 Endpoint activation

The endpoint is maintained under reset as long as the EPEN bit is not set.

The following flow must be respected in order to activate an endpoint:

AT90USB646 Datasheet(PDF) 270 Page - ATMEL Corporation