Electronic Components Datasheet Search
  English  ▼

X  

AT90USB646 Datasheet(PDF) 274 Page - ATMEL Corporation

Part # AT90USB646
Description  Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
PDF  434 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90USB646 Datasheet(HTML) 274 Page - ATMEL Corporation

Back Button AT90USB646 Datasheet HTML 270Page - ATMEL Corporation AT90USB646 Datasheet HTML 271Page - ATMEL Corporation AT90USB646 Datasheet HTML 272Page - ATMEL Corporation AT90USB646 Datasheet HTML 273Page - ATMEL Corporation AT90USB646 Datasheet HTML 274Page - ATMEL Corporation AT90USB646 Datasheet HTML 275Page - ATMEL Corporation AT90USB646 Datasheet HTML 276Page - ATMEL Corporation AT90USB646 Datasheet HTML 277Page - ATMEL Corporation AT90USB646 Datasheet HTML 278Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 274 / 434 page
background image
274
7593A–AVR–02/06
AT90USB64/128
22.12.2
STALL handshake and Retry mechanism
The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ request bit is set and if there is no retry required.
22.13 CONTROL endpoint management
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-
rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall
thus never use them on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
acknowledge the packet
and to clear the endpoint bank.
• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
acknowledge the packet
and to clear the endpoint bank.
• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware
to
send the packet and to clear the endpoint bank.
CONTROL endpoints should not be managed by interrupts, but only by polling the status bits.
22.13.1
Control Write
The next figure shows a control write transaction. During the status stage, the controller will not
necessary send a NAK at the first IN token:
• If the firmware knows the exact number of descriptor bytes that must be read, it can then
anticipate on the status stage and send a ZLP for the next IN token,
• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the
host, and the transaction is now in the status stage.
SETUP
RXSTPI
RXOUTI
TXINI
USB line
HW
SW
OUT
HW
SW
OUT
HW
SW
IN
IN
NAK
SW
DATA
SETUP
STATUS



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com