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AT90USB646 Datasheet(PDF) 333 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 333 Page - ATMEL Corporation |
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333 / 434 page  333 7593A–AVR–02/06 AT90USB64/128 25.8.3.2 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 327. 25.8.4 ADC Control and Status Register B – ADCSRB • Bit 7 – ADHSM: ADC High Speed Mode Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion rate at the expense of higher power consumption. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set . Bit 151413121110 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 – –––– – ADCL Bit 765 4321 0 Read/Write RRRR RRRR RRRR RRRR Initial Value 000 0000 0 000 0000 0 Bit 7 65 432 10 ADHSM ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 25-6. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter0 Compare Match |
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