AT90USB646 datasheet(381/434 Pages) ATMEL

381 / 434 page

381

7593A–AVR–02/06

AT90USB64/128

29.6.15

Parallel Programming Characteristics

Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements

Figure 29-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)

Note:

1. The timing requirements shown in Figure 29-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-

ing operation.

Figure 29-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements

(1)

Data & Contol

(DATA, XA0/1, BS1, BS2)

XTAL1

XHXL

WLWH

DVXH

XLDX

PLWL

WLRH

RDY/BSY

PAGEL

PHPL

PLBX

BVPH

XLWL

WLBX

BVWL

WLRL

XTAL1

PAGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

XTAL1

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

AT90USB646 Datasheet(PDF) 381 Page - ATMEL Corporation

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