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RECEIVE AC TIMING Figure 6

TRANSMIT AC TIMING Figure 7

NOTE: When TDIS is high about the rising edge of TCLK, TDATA will not be updated and will be held with the previous valve until TDIS is low

about the rising edge of TCLK.

TRANSMIT AC TIMING FOR THE TL INPUT Figure 8

NOTE: The rising edge of TL causes the internal pattern generation circuitry to be reloaded; the first bit of the new pattern (the shaded one) will

appear after two TCLK periods.