DS2153Q datasheet(39/60 Pages) MAXIM

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DS2153Q

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13 LINE INTERFACE FUNCTIONS

The line interface function in the DS2153Q contains three sections: the receiver, which handles clock and

data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of

these three sections is controlled by the Line Interface Control Register (LICR), which is described

below.

LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex)

(MSB)

(LSB)

LB2

LB1

LB0

EGL

JAS

JABDS

DJA

TPD

LICR

SYMBOL POSITION NAME AND DESCRIPTION

LB2

LICR.7

Line Build-Out Select Bit 2. Sets the transmitter build

out; see the Table 13-2.

LB1

LICR.6

Line Build-Out Select Bit 1. Sets the transmitter build

out; see the Table 13-2.

LB0

LICR.5

Line Build-Out Select Bit 0. Sets the transmitter build

out; see the Table 13-2.

EGL

LICR.4

Receive Equalizer Gain Limit.

0 = -12dB

1 = -30dB

JAS

LICR.3

Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

JABDS

LICR.2

Jitter Attenuator Buffer Depth Select.

0 = 128 bits

1 = 32 bits (use for delay sensitive applications)

DJA

LICR.1

Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

TPD

LICR.0

Transmit Power Down.

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP

and TRING pins

DS2153Q Datasheet(PDF) 39 Page - Maxim Integrated Products

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