LTC4012 datasheet(10/52 Pages) AD

10 / 52 page

LTC4162-L

Rev A

For more information www.analog.com

PIN FUNCTIONS

BOOST (Pin 1): Gate-Drive bias for the high side switch in

the switching regulator. This pin provides a pumped bias

voltage relative to SW. The voltage on this pin is charged

up through an internal diode from INTVCC. A 22nF multi-

layer ceramic capacitor is required from SW to BOOST.

INTVCC (Pin 2): Bypass pin for the internal 5V regulator.

This regulator provides power to the internal analog cir-

cuitry. A 4.7µF multilayer ceramic capacitor is required

from INTVCC to GND.

VOUTA (Pin 3): Analog system power pin. VOUTA powers

the majority of circuits on the LTC4162. A 0.1µF multilayer

ceramic capacitor is required from VOUTA to GND.

CLN (Pin 4): Connection point for the negative terminal

of the sense resistor that measures and regulates input

current by limiting charge current.

CLP (Pin 5): Connection point for the positive terminal

of the sense resistor that measures and regulates input

current by limiting charge current.

INFET (Pin 6): Gate control output pin for an input reverse

blocking external N-channel MOSFET between VIN and

VOUT.

VIN (Pin 7): Supply voltage detection and INFET charge

pump supply for the INFET/BATFET PowerPath. When

voltage at VIN is detected as being high enough to charge a

battery,theINFETcharge-pumpisactivatedandtheBATFET

charge-pump is deactivated thereby powering VOUTA from

the input supply through an external NMOS transistor and

also starting a charge cycle. A 0.1µF multilayer ceramic

capacitor is required from VIN to GND.

VCC2P5 (Pin 8): Bypass pin for the internal 2.5V regula-

tor. This regulator provides power to the internal logic

circuitry. A 1µF multilayer ceramic capacitor is required

from VCC2P5 to GND.

NTCBIAS (Pin 9): NTC thermistor bias output. Connect a

lowtemperaturecoefficientbiasresistorbetweenNTCBIAS

and NTC, and a thermistor between NTC and GND. The

bias resistor should be equal in value to the nominal value

of the thermistor. The LTC4162 applies 1.2V to this pin

during NTC measurement and expects a thermistor β

value of 3490K. Higher β value thermistors can be used

with simple circuit modifications.

NTC (Pin 10): Thermistor input. The NTC pin connects to

a negative temperature coefficient thermistor to monitor

the temperature of the battery. The voltage on this pin

is digitized by the analog to digital converter to qualify

battery charging and is available for readout via the I2C

port. A low drift bias resistor is required from NTCBIAS

to NTC and a thermistor is required from NTC to ground.

RT (Pin 11): Switching regulator frequency control pin.

The RT pin controls the switching regulator's internal

oscillator frequency by placing a resistor from RT to GND.

SMBALERT (Pin 12): Interrupt output. This open drain

output pulls low when one or more of the programmable

alerts is triggered.

SCL (Pin 13): Open drain clock input for the I2C port. The

I2C port input levels are scaled with respect to DVCC for

I2C compliance.

SDA (Pin 14): Open drain data input/output for the I2C

port. The I2C port input levels are scaled with respect to

DVCC for I2C compliance.

DVCC (Pin 15): Logic supply for the I2C port. DVCC sets the

reference level of the SDA and SCL pins for I2C compli-

ance. It should be connected to the same power supply

as the SDA and SCL pull up resistors.

SYNC(Pin16):Optionalexternalclockinputfortheswitch-

ing battery charger. The switching battery charger will

lock to a square wave or pulse on this pin that is close to

the frequency programmed by the RT pin. Ground SYNC

if this feature is not needed.

LTC4012 Datasheet(PDF) 10 Page - Analog Devices

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