MSM60808 datasheet(21/92 Pages) OKI

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MSM60808

4.3 CardBus Interface Signals

Table 4.2 CardBus Interface Signals

Signal Name

I/O

CardBus clock signal. All CardBus signals except CRST#, CCLKRUN#, CINT#,

CSTSCHG, CAUDIO, CCD1#, CCD2#, CVS1#, and CVS2# are synchronized to the

rising edge of CCLK. The CardBus clock is 33 MHz, but the clock can also be stopped

by driving it low.

CardBus address/data bus signals. Address and data are multiplexed on the same

pins. During the first clock of a transaction CAD[31:0] carry a physical address

(32 bits). During the following clocks CAD[31:0] carry data.

Command and byte enable signals. During the address phase of a transaction

CC/BE#[3:0] define the bus command. During the data phase CC/BE#[3:0] are used

as byte enables.

CardBus cycle frame signal. CFRAME# is driven by the master to indicate the start

and duration of a bus cycle. CFRAME# is asserted to indicate the start of a bus cycle.

Bus cycles continue while CFRAME# stays asserted. CFRAME# is deasserted to

indicate that the next data phase is the final data phase.

CardBus device select signal. When the MSM60808 is the target, it will respond to

bus cycles where CDEVSEL# is asserted. When the MSM60808 is the master, it

monitors CDEVSEL# to determine whether or not the target has responded.

Description

CCLK

OUT

CAD[31:0]

T/S

CFRAME#

S/T/S

CDEVSEL#

S/T/S

CardBus clock run signal. A CardBus card asserts CCLKRUN# to request the

MSM60808 clock. The MSM60808 asserts CCLKRUN# while it outputs the clock,

and puts the pin in high impedance if it stops the clock.

CCLKRUN#

T/S

CardBus reset signal. CRST# operates asynchronously to CCLK.

CRST#

OUT

CC/BE#[3:0]

T/S

CardBus parity signal. CPAR provides even parity across CAD[31:0] and CC/BE#[3:0].

Address parity is driven by the master that started the bus cycle one clock after the

address phase. In the data phase, the master calculates parity and drives CPAR for

write cycles, and the target does so for read cycles. Just like the address phase, in the

data phase parity for data is output delayed by one clock.

CPAR

T/S

CardBus initiator ready signal. CIRDY# indicates that the master is ready to perform a

transfer. CIRDY# is used in conjunction with CTRDY#. Data transfers are timed to

execute when both CIRDY# and CTRDY# are asserted. During write cycles CIRDY#

indicates that valid data is on CAD[31:0]. During read cycles CIRDY# indicates that

the device is ready to accept read data. Wait cycles are inserted until both CIRDY#

and CTRDY# are asserted together.

CIRDY#

S/T/S

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