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ES9219 Datasheet(PDF) 56 Page - ESS Technology,Inc

Part # ES9219
Description  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  67 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9219 Datasheet(HTML) 56 Page - ESS Technology,Inc

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ES9219 Datasheet
February 27, 2020
CONFIDENTIAL ADVANCE INFORMATION 1.0.4
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
56
Register 136: DRE CONFIG
I2C Slave Access:
I2S Sync Slave Access:
Clock Domain:
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Mnemo
nic
DRE_FOR
CE2
DRE_FOR
CE1
DRE_ENABLE_PEAK_
FILTER
DRE_VOLUME_
CTRL
DRE_ATR_DI
SABLE
RESERVE
D
RESERV
ED
ENABLE_
DRE
Bits
Mnemonic
Description
[7]
DRE_FORCE2
Force Channel 2 into DRE mode even if zero cross has not occurred.
1’b1: Enable
1’b0: Disable
[6]
DRE_FORCE1
Force Channel 1 into DRE mode even if zero cross has not occurred.
1’b1: Enable
1’b0: Disable
[5]
DRE_ENABLE_PEAK_FILTER
Low Pass filter the input to the DRE peak detector, for use with DSD inputs.
1’b1: Enable
1’b0: Disable
[4]
DRE_VOLUME_CTRL
When enabled, the analog volume control and digital gain will be adjusted to optimize
output performance in DRE mode.
1’b0: The analog volume control will not be affected by the DRE (default).
1’b1: The analog volume control will be set to its minimum value when the DRE mode is
engaged. A digital gain will be applied in this mode of operation to ensure the total gain
of the DAC is nominal at 0dB.
[3]
DRE_ATR_DISABLE
1’b0: Analog THD removal (ATR) will not be disabled by the DRE block (default).
1’b1: Disable analog THD removal (ATR) when DRE is engaged.
[2]
RESERVED
NA
[1]
RESERVED
NA
[0]
ENABLE_DRE
Selects whether the DRE module is enabled.
1’b0: DRE module is disabled and DRE mode will never be engaged (default).
1’b1: DRE module is enabled and DRE mode will be engaged if the stored value in the
peak detector falls below the specified DRE threshold.
Register 137-138: DRE GAIN CH1
I2C Slave Access:
I2S Sync Slave Access:
Clock Domain:
Bits
[15:0]
Mnemonic
DRE_GAIN1
Bits
Mnemonic
Description
[15:0]
DRE_GAIN1
Sets the DRE gain for channel 1.
Shifting right 1 bit corresponds to -6dB
Valid from 16’h7FFF (30dB) to 16’h03FF (0dB)



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