TMUX6209 datasheet(32/51 Pages) TI

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9.3.6 Latch-Up Immune

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide

layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures

from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events

due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches

and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using

Latch Up Immune Multiplexers to Help Improve System Reliability.

9.3.7 Ultra-Low Charge Injection

Figure 9-1 shows that the TMUX620x have a transmission gate topology. Any mismatch in the stray capacitance

associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

GDP

GDN

GSN

GSP

OFF

OFF ON

Figure 9-1. Transmission Gate Topology

The TMUX620x contain specialized architecture to reduce charge injection on the Drain (D). To further reduce

charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This

will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the

Source (Sx) instead of the Drain (D). As a general rule of thumb, Cp should be 20x larger than the equivalent

load capacitance on the Drain (D). Figure 9-2 shows charge injection variation with different compensation

capacitors on the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a

100pF load capacitance.

Figure 9-2. Charge Injection Compesation

TMUX6208, TMUX6209

SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021

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TMUX6209 Datasheet(PDF) 32 Page - Texas Instruments