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ISO6763FDWR Datasheet(PDF) 25 Page - Texas Instruments |
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ISO6763FDWR Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 44 page ![]() 9.2 Typical Application Figure 9-1 shows the isolated connections between a processor and Intelligent Power Module (IPM) interface implementation. 10 μF 10 μF D2 SN6505 D1 GND 24V IN EN GND OUT LDO 10 μF 15V_ISO Vcc 0.1 μF CONTROLLER VL VSS VDDIO WL IN GND OUT LDO 1 µF VCC1 VCC2 GND1 GND2 INA_H INC_L INA_L INB_H OUTA_H OUTB_H OUTC_L INC_H INB_L ISO6760L OUTC_H OUTA_L OUTB_L UL WH VH UH 0.1 μF 0.1 μF 1 2 4 6 7 3 5 8 9 12 14 10 11 13 15 16 Signal Level shift + Bias Supply Bootstrap High side gate driver High side gate driver High side gate driver 3 phase IGBT inverter Low side gate driver M 5V_ISO IPM with SIGNAL LEVEL-SHIFT and BOOTSTRAP for GATE DRIVER BIAS SUPPLY HV DC+ DC-DC 5.0V EN U V W 15V_ISO HV DC- VLIN WLIN ULIN WHIN VHIN UHIN HV DC- 5.0V Figure 9-1. Isolation for Intelligent Power Module (IPM) Interface www.ti.com ISO6760L SLLSFO3 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: ISO6760L |
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