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AD7658 Datasheet(PDF) 9 Page - Analog Devices |
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AD7658 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 25 page  Preliminary Technical Data AD7658/AD7657/AD7656 Rev. PrI | Page 9 of 25 TIMING SPECIFICATIONS1 Table 4. AVCC = 4.5 V to 5.5 V, VDD = 9.5 V to 16.5 V, VSS = -9.5 V to -16.5V, VDRIVE = 2.7V to 5.25V; TA = TMIN to TMAX, unless otherwise noted Limit at TMIN, TMAX Parameter 5 V Unit Description Parallel Mode tCONVERT 3 µs typ Conversion Time, Internal Clock tQUIET 400 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 3 ns min CONVST high to BUSY high Twake-up TBD ns typ STBY rising edge to CONVST rising edge Write Operation t13 0 ns min CS to WR setup time t14 0 ns min CS to WR Hold time t12 20 ns min WR Pulse width t15 5 ns min Data setup time before WR rising edge t12/14/16 5 ns min Data hold after WR rising edge Read Operation t2 0 ns min BUSY to RD Delay t3 0 ns min CS to RD setup time t4 0 ns min CS to RD Hold time t5 30 ns min RD Pulse width t6 30 ns max Data access time after RD falling edge t7 15 ns min Bus relinquish time after RD rising edge 25 ns max t9 20 ns min Minimum time between reads Serial Interface fSCLK 20 MHz max Frequency of Serial Read Clock t17 10 ns max CS to SCLK setup time t18 15 ns max Delay from CS until SDATA three-state disabled t19 20 ns max Data access time after SCLK rising edge t20 0.4 tSCLK ns min SCLK low pulse width t21 0.4 tSCLK ns min SCLK high pulse width t22 5 ns min SCLK to data valid hold time t23 30 ns max CS rising edge to SDATA high impedance 200 µAI OL 200 µAI OH 1.6V TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output Timing Specification 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. |
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