TPS22916CLYFPR datasheet(20/29 Pages) TI

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11 Layout

11.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output

capacitors must be placed close to the device to minimize the effects that parasitic trace inductances can have

on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects.

11.2 Layout Example

Equation 3 shows an example for these devices. Notice the connection to system ground between the VOUT

Bypass Capacitor ground and the GND pin of the load switch,. This connection creates a ground barrier which

helps to reduce the ground noise seen by the device.

Gnd

Via

VIA to Power Ground Plane

V Bypass

Capacitor

Bypass

Capacitor

OUT

To GPIO

control

VOUT

VIN

GND

Gnd

Via

Figure 11-1. TPS22916xx Layout

11.3 Thermal Considerations

The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To

calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use

Equation 5 as a guideline:

J(MAX)

D(MAX)

θJA

(5)

Where,

PD(max) = maximum allowable power dissipation

TJ(max) = maximum allowable junction temperature

TA = ambient temperature for the device

θJA = junction to air thermal impedance. See the Thermal Information section.

TPS22916

SLVSDO5F – JULY 2017 – REVISED DECEMBER 2021

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