LT3758 datasheet(14/28 Pages) AD

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LT8392

Rev. 0

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OPERATION

Main Control Loop

The LT8392 is a fixed frequency current mode control-

ler. The inductor current is sensed through the inductor

sense resistor between the LSP and LSN pins. The current

sense voltage is gained up by amplifier A1 and added

to a slope compensation ramp signal from the internal

oscillator. The summing signal is then fed into the positive

terminals of the buck current comparator A3 and boost

current comparator A4. The negative terminals of A3 and

A4 are controlled by the voltage on the VC pin, which is

the diode-OR of error amplifiers EA1 and EA2.

Depending on the state of the peak-buck peak-boost cur-

rent mode control, either the buck logic or the boost logic

is controlling the four power switches so that either the

FB voltage is regulated to 1V or the current sense voltage

between the ISP and ISN pins is regulated by the CTRL

pin during normal operation. The gains of EA1 and EA2

have been balanced to ensure smooth transition between

constant-voltage and constant-current operation with the

same compensation network.

Light Load Current Operation

At light load, the LT8392 runs either at full switching fre-

quency discontinuous conduction mode or pulse-skip-

ping mode, where the switches are held off for multiple

cycles (i.e., skipping pulses) to maintain the regulation

and improve the efficiency.

In the buck region, switch B is turned off whenever the

buck reverse current threshold is triggered during (B+D)

phase. In the boost region, switch D is turned off when-

ever the boost reverse current threshold is triggered

during (A+D) phase. In the buck-boost region, switch D

is turned off whenever the boost reverse current thresh-

old is triggered during (A+D) phase, and both switches B

and D are turned off whenever the buck reverse current

threshold is triggered during (B+D) phase.

Internal Charge Path

Each of the two top MOSFET drivers is biased from its

floating bootstrap capacitor, which is normally re-charged

by INTVCC through both the external and internal boot-

strap diodes when the top MOSFET is turned off. When

the LT8392 operates exclusively in the buck or boost

regions, one of the top MOSFETs is constantly on. An

internal charge path, from VOUT and BST2 to BST1 or from

VIN and BST1 to BST2, charges the bootstrap capacitor to

4.6V so that the top MOSFET can be kept on.

Shutdown and Power-On-Reset

The LT8392 enters shutdown mode and drains less than

2µA quiescent current when the EN/UVLO pin is below

its shutdown threshold (0.3V minimum). Once the EN/

UVLO pin is above its shutdown threshold (1V maximum),

the LT8392 wakes up startup circuitry, generates band-

gap reference, and powers up the internal INTVCC LDO.

The INTVCC LDO supplies the internal control circuitry

and gate drivers. Now the LT8392 enters undervoltage

lockout (UVLO) mode with a hysteresis current (2.5µA

typical) pulled into the EN/UVLO pin. When the INTVCC pin

is charged above its rising UVLO threshold (3.76V typi-

cal), the EN/UVLO pin passes its rising enable threshold

(1.233V typical), and the junction temperature is less than

its thermal shutdown (165°C typical), the LT8392 enters

enable mode, in which the EN/UVLO hysteresis current is

turned off and the voltage reference VREF is being charged

up from ground. From the time of entering enable mode to

the time of VREF passing its rising UVLO threshold (1.89V

typical), the LT8392 is going through a power-on-reset

(POR), waking up the entire internal control circuitry and

settling to the right initial conditions. After the POR, the

LT8392 starts switching.

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